devicetree/bindings/xilinx.txt

10    Each IP-core has a set of parameters which the FPGA designer can use to
20    properties of the device node.  In general, device nodes for IP-cores
23 	(name): (generic-name)@(base-address) {
24 		compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 		interrupt-parent = <&interrupt-controller-phandle>;
29 		xlnx,(parameter1) = "(string-value)";
30 		xlnx,(parameter2) = <(int-value)>;
33 	(generic-name):   an open firmware-style name that describes the
36 	(ip-core-name):	the name of the ip block (given after the BEGIN
38 			and all underscores '_' converted to dashes '-'.
43 			converted to dashes '-'.
46 	(size):		the address range size (often C_HIGHADDR - C_BASEADDR + 1).
52    'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
78 		compatible = "xlnx,opb-uartlite-1.00.b";
80 		interrupt-parent = <&opb_intc_0>;
82 		current-speed = <d#115200>;	// standard serial device prop
83 		clock-frequency = <d#50000000>;	// standard serial device prop
84 		xlnx,data-bits = <8>;
85 		xlnx,odd-parity = <0>;
86 		xlnx,use-parity = <0>;
92    ranges property can be used to translate from parent IP-core to the
95    #address-cells and #size-cells, as with any other bus.  (Note: this
98    for each logical device).  The 'cell-index' property can be used to
123 	opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
124 		#address-cells = <1>;
125 		#size-cells = <1>;
131 			compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
133 			interrupt-parent = <&opb_intc_0>;
135 			cell-index = <0>;
138 			compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
140 			interrupt-parent = <&opb_intc_0>;
142 			cell-index = <0>;
204 		#address-cells = <1>;
205 		#size-cells = <1>;
206 		compatible = "xlnx,plb-v34-1.02.a";
215 			#address-cells = <1>;
216 			#size-cells = <1>;
226 			opb_intc_0: interrupt-controller@d1000fc0 {
235       i) Xilinx ML300 Framebuffer
237       Simple framebuffer device from the ML300 reference design (also on the
241        - resolution = <xres yres> : pixel resolution of framebuffer.  Some
244        - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
246        - rotate-display (empty) : rotate display 180 degrees.
255        - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
260       listed above, nodes for these devices should include a phy-handle
262       like local-mac-address.
266       Xilinx uartlite devices are simple fixed speed serial ports.
269        - current-speed : Baud rate of uartlite
280 		- xlnx,family : The family of the FPGA, necessary since the
291        - clock-frequency : Frequency of the clock input
292        - reg-offset : A value of 3 is required
293        - reg-shift : A value of 2 is required
298       base address for the EHCI registers, and it is always a big-endian
303       - xlnx,support-usb-fs: A value 0 means the core is built as high speed