Lines Matching full:1
40 #define TEST_ASSERT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 1, __abort_test, "")
42 __TEST_EQ(a, b, #a, #b, 1, __abort_test, fmt, ## args)
46 u32 shadow_vmcs:1;
84 u32 reserved16 : 1;
85 u32 reserved17 : 1;
86 u32 reserved18 : 1;
87 u32 reserved19 : 1;
88 u32 reserved20 : 1;
89 u32 reserved21 : 1;
90 u32 reserved22 : 1;
91 u32 reserved23 : 1;
92 u32 reserved24 : 1;
93 u32 reserved25 : 1;
94 u32 reserved26 : 1;
95 u32 enclave_mode : 1;
96 u32 smi_pending_mtf : 1;
97 u32 smi_from_vmx_root : 1;
98 u32 reserved30 : 1;
99 u32 failed_vmentry : 1;
139 width:1,
140 dual:1,
142 insouts:1,
143 ctrl:1,
144 no_hw_errcode_cc:1,
160 stores_lma:1,
161 act_hlt:1,
162 act_shutdown:1,
163 act_wfsipi:1,
165 vmx_pt:1,
166 smm_smbase:1,
169 smm_mon_ctl:1,
170 vmwrite_any:1,
171 inject_len0:1,
172 :1;
183 invept:1,
185 u32 invvpid:1;
375 #define VMX_ENTRY_FAILURE (1ul << 31)
381 VMX_EXTINT = 1,
443 EXI_SAVE_DBGCTLS = 1UL << 2,
444 EXI_HOST_64 = 1UL << 9,
445 EXI_LOAD_PERF = 1UL << 12,
446 EXI_INTA = 1UL << 15,
447 EXI_SAVE_PAT = 1UL << 18,
448 EXI_LOAD_PAT = 1UL << 19,
449 EXI_SAVE_EFER = 1UL << 20,
450 EXI_LOAD_EFER = 1UL << 21,
451 EXI_SAVE_PREEMPT = 1UL << 22,
455 ENT_LOAD_DBGCTLS = 1UL << 2,
456 ENT_GUEST_64 = 1UL << 9,
457 ENT_LOAD_PERF = 1UL << 13,
458 ENT_LOAD_PAT = 1UL << 14,
459 ENT_LOAD_EFER = 1UL << 15,
460 ENT_LOAD_BNDCFGS = 1UL << 16
464 PIN_EXTINT = 1ul << 0,
465 PIN_NMI = 1ul << 3,
466 PIN_VIRT_NMI = 1ul << 5,
467 PIN_PREEMPT = 1ul << 6,
468 PIN_POST_INTR = 1ul << 7,
472 CPU_INTR_WINDOW = 1ul << 2,
473 CPU_USE_TSC_OFFSET = 1ul << 3,
474 CPU_HLT = 1ul << 7,
475 CPU_INVLPG = 1ul << 9,
476 CPU_MWAIT = 1ul << 10,
477 CPU_RDPMC = 1ul << 11,
478 CPU_RDTSC = 1ul << 12,
479 CPU_CR3_LOAD = 1ul << 15,
480 CPU_CR3_STORE = 1ul << 16,
481 CPU_CR8_LOAD = 1ul << 19,
482 CPU_CR8_STORE = 1ul << 20,
483 CPU_TPR_SHADOW = 1ul << 21,
484 CPU_NMI_WINDOW = 1ul << 22,
485 CPU_IO = 1ul << 24,
486 CPU_IO_BITMAP = 1ul << 25,
487 CPU_MTF = 1ul << 27,
488 CPU_MSR_BITMAP = 1ul << 28,
489 CPU_MONITOR = 1ul << 29,
490 CPU_PAUSE = 1ul << 30,
491 CPU_SECONDARY = 1ul << 31,
495 CPU_VIRT_APIC_ACCESSES = 1ul << 0,
496 CPU_EPT = 1ul << 1,
497 CPU_DESC_TABLE = 1ul << 2,
498 CPU_RDTSCP = 1ul << 3,
499 CPU_VIRT_X2APIC = 1ul << 4,
500 CPU_VPID = 1ul << 5,
501 CPU_WBINVD = 1ul << 6,
502 CPU_URG = 1ul << 7,
503 CPU_APIC_REG_VIRT = 1ul << 8,
504 CPU_VINTD = 1ul << 9,
505 CPU_RDRAND = 1ul << 11,
506 CPU_SHADOW_VMCS = 1ul << 14,
507 CPU_RDSEED = 1ul << 16,
508 CPU_PML = 1ul << 17,
509 CPU_USE_TSC_SCALING = 1ul << 25,
532 #define INTR_TYPE_RESERVED (1 << 8) /* reserved */
543 #define GUEST_INTR_STATE_STI (1 << 0)
544 #define GUEST_INTR_STATE_MOVSS (1 << 1)
545 #define GUEST_INTR_STATE_SMI (1 << 2)
546 #define GUEST_INTR_STATE_NMI (1 << 3)
547 #define GUEST_INTR_STATE_ENCLAVE (1 << 4)
553 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
627 #define _VMX_IO_WORD 1
629 #define VMX_IO_DIRECTION_MASK (1ul << 3)
630 #define VMX_IO_IN (1ul << 3)
632 #define VMX_IO_STRING (1ul << 4)
633 #define VMX_IO_REP (1ul << 5)
634 #define VMX_IO_OPRAND_IMM (1ul << 6)
639 #define VMX_TEST_VMEXIT 1
645 #define HYPERCALL_BIT (1ul << 12)
655 #define EPTP_AD_FLAG (1ul << 6)
658 #define EPT_MEM_TYPE_WC 1ul
663 #define EPT_RA 1ul
667 #define EPT_ACCESS_FLAG (1ul << 8)
668 #define EPT_DIRTY_FLAG (1ul << 9)
669 #define EPT_LARGE_PAGE (1ul << 7)
672 #define EPT_IGNORE_PAT (1ul << 6)
673 #define EPT_SUPPRESS_VE (1ull << 63)
675 #define EPT_CAP_EXEC_ONLY (1ull << 0)
676 #define EPT_CAP_PWL4 (1ull << 6)
677 #define EPT_CAP_PWL5 (1ull << 7)
678 #define EPT_CAP_UC (1ull << 8)
679 #define EPT_CAP_WB (1ull << 14)
680 #define EPT_CAP_2M_PAGE (1ull << 16)
681 #define EPT_CAP_1G_PAGE (1ull << 17)
682 #define EPT_CAP_INVEPT (1ull << 20)
683 #define EPT_CAP_AD_FLAG (1ull << 21)
684 #define EPT_CAP_ADV_EPT_INFO (1ull << 22)
685 #define EPT_CAP_INVEPT_SINGLE (1ull << 25)
686 #define EPT_CAP_INVEPT_ALL (1ull << 26)
687 #define VPID_CAP_INVVPID (1ull << 32)
688 #define VPID_CAP_INVVPID_ADDR (1ull << 40)
689 #define VPID_CAP_INVVPID_CXTGLB (1ull << 41)
690 #define VPID_CAP_INVVPID_ALL (1ull << 42)
691 #define VPID_CAP_INVVPID_CXTLOC (1ull << 43)
698 #define EPT_PGDIR_ENTRIES (1 << EPT_PGDIR_WIDTH)
699 #define EPT_LEVEL_SHIFT(level) (((level)-1) * EPT_PGDIR_WIDTH + 12)
701 #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1))
703 #define EPT_VLT_RD (1ull << 0)
704 #define EPT_VLT_WR (1ull << 1)
705 #define EPT_VLT_FETCH (1ull << 2)
706 #define EPT_VLT_PERM_RD (1ull << 3)
707 #define EPT_VLT_PERM_WR (1ull << 4)
708 #define EPT_VLT_PERM_EX (1ull << 5)
709 #define EPT_VLT_PERM_USER_EX (1ull << 6)
712 #define EPT_VLT_LADDR_VLD (1ull << 7)
713 #define EPT_VLT_PADDR (1ull << 8)
714 #define EPT_VLT_GUEST_USER (1ull << 9)
715 #define EPT_VLT_GUEST_RW (1ull << 10)
716 #define EPT_VLT_GUEST_EX (1ull << 11)
725 #define INVEPT_SINGLE 1
729 #define INVVPID_CONTEXT_GLOBAL 1
734 #define ACTV_HLT 1
741 * Bits 1-9: Index
747 #define VMCS_FIELD_INDEX_SHIFT (1)
748 #define VMCS_FIELD_INDEX_MASK GENMASK(9, 1)
825 (ctrl_cpu_rev[1].clr & CPU_VPID); in is_vpid_supported()
848 /* -1 on VM-Fail, 0 on success, >1 on fault */
854 asm volatile ("push %1\n\t" in __vmxon_safe()
856 ASM_TRY("1f") "vmxon %2\n\t" in __vmxon_safe()
859 "1: movb $0, %0\n\t" in __vmxon_safe()
864 return -1; in __vmxon_safe()
884 asm volatile("push %1; popf; vmxoff; setbe %0\n\t" in vmx_off()
894 asm volatile ("push %1; popf; vmptrld %2; setbe %0" in make_vmcs_current()
904 asm volatile ("push %1; popf; vmclear %2; setbe %0" in vmcs_clear()
912 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); in vmcs_read()
924 asm volatile ("vmread %1, %0" : "=m" (val) : "r" ((u64)enc) : "cc"); in vmcs_readm()
950 asm volatile ("vmwrite %1, %2; setbe %0" in vmcs_write()
971 asm volatile ("push %2; popf; vmptrst %1; setbe %0" in vmcs_save()
973 *vmcs = (pa == -1ull) ? NULL : phys_to_virt(pa); in vmcs_save()
985 asm volatile("push %1; popf; invept %2, %3; setbe %0" in __invept()
987 return failed ? -1: 0; in __invept()
1001 asm volatile("push %1; popf; invvpid %2, %3; setbe %0" in __invvpid()
1003 return failed ? -1: 0; in __invvpid()