Lines Matching refs:ctrl_cpu_rev
71 union vmx_ctrl_msr ctrl_cpu_rev[2]; variable
1104 if (ctrl_cpu_rev[0].set & CPU_SECONDARY) { in init_vmcs_ctrl()
1105 ctrl_cpu[1] = (ctrl_cpu[1] | ctrl_cpu_rev[1].set) & in init_vmcs_ctrl()
1106 ctrl_cpu_rev[1].clr; in init_vmcs_ctrl()
1261 ctrl_cpu[0] = (ctrl_cpu[0] | ctrl_cpu_rev[0].set) & ctrl_cpu_rev[0].clr; in init_vmcs()
1291 ctrl_cpu_rev[0].val = rdmsr(basic_msr.ctrl ? MSR_IA32_VMX_TRUE_PROC in init_vmx_caps()
1293 if ((ctrl_cpu_rev[0].clr & CPU_SECONDARY) != 0) in init_vmx_caps()
1294 ctrl_cpu_rev[1].val = rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2); in init_vmx_caps()
1296 ctrl_cpu_rev[1].val = 0; in init_vmx_caps()
1297 if ((ctrl_cpu_rev[1].clr & (CPU_EPT | CPU_VPID)) != 0) in init_vmx_caps()
1604 report((!(ctrl_cpu_rev[1].clr & CPU_URG) || val & (1ul << 5)) && in test_vmx_caps()