Lines Matching full:1

55         VMCB_CLEAN_INTERCEPTS = 1, /* Intercept vectors, TSC offset, pause filter count */
112 #define TLB_CONTROL_FLUSH_ALL_ASID 1
117 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
120 #define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT)
123 #define V_GIF_MASK (1 << V_GIF_SHIFT)
129 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
132 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
135 #define V_NMI_PENDING_MASK	(1 << V_NMI_PENDING_SHIFT)
137 #define V_NMI_BLOCKING_MASK	(1 << V_NMI_BLOCKING_SHIFT)
139 #define V_NMI_ENABLE_MASK	(1 << V_NMI_ENABLE_SHIFT)
141 #define SVM_INTERRUPT_SHADOW_MASK 1
148 #define SVM_IOIO_TYPE_MASK 1
149 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
150 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
231 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
233 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
234 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
235 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
236 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
237 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
239 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
241 #define SVM_SELECTOR_CODE_MASK (1 << 3)
243 #define INTERCEPT_CR0_MASK 1
244 #define INTERCEPT_CR3_MASK (1 << 3)
245 #define INTERCEPT_CR4_MASK (1 << 4)
246 #define INTERCEPT_CR8_MASK (1 << 8)
248 #define INTERCEPT_DR0_MASK 1
249 #define INTERCEPT_DR1_MASK (1 << 1)
250 #define INTERCEPT_DR2_MASK (1 << 2)
251 #define INTERCEPT_DR3_MASK (1 << 3)
252 #define INTERCEPT_DR4_MASK (1 << 4)
253 #define INTERCEPT_DR5_MASK (1 << 5)
254 #define INTERCEPT_DR6_MASK (1 << 6)
255 #define INTERCEPT_DR7_MASK (1 << 7)
267 #define SVM_EVTINJ_VALID (1 << 31)
268 #define SVM_EVTINJ_VALID_ERR (1 << 11)
357 #define SVM_EXIT_ERR		-1