Lines Matching +full:0 +full:x80
111 #define TLB_CONTROL_DO_NOTHING 0
114 #define V_TPR_MASK 0x0f
126 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
154 #define SVM_VM_CR_VALID_MASK 0x001fULL
155 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
156 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
158 #define TSC_RATIO_DEFAULT 0x0100000000ULL
218 #define SVM_CPUID_FUNC 0x8000000a
230 #define SVM_SELECTOR_TYPE_MASK (0xf)
257 #define SVM_EVTINJ_VEC_MASK 0xff
262 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
285 #define SVM_EXIT_READ_CR0 0x000
286 #define SVM_EXIT_READ_CR3 0x003
287 #define SVM_EXIT_READ_CR4 0x004
288 #define SVM_EXIT_READ_CR8 0x008
289 #define SVM_EXIT_WRITE_CR0 0x010
290 #define SVM_EXIT_WRITE_CR3 0x013
291 #define SVM_EXIT_WRITE_CR4 0x014
292 #define SVM_EXIT_WRITE_CR8 0x018
293 #define SVM_EXIT_READ_DR0 0x020
294 #define SVM_EXIT_READ_DR1 0x021
295 #define SVM_EXIT_READ_DR2 0x022
296 #define SVM_EXIT_READ_DR3 0x023
297 #define SVM_EXIT_READ_DR4 0x024
298 #define SVM_EXIT_READ_DR5 0x025
299 #define SVM_EXIT_READ_DR6 0x026
300 #define SVM_EXIT_READ_DR7 0x027
301 #define SVM_EXIT_WRITE_DR0 0x030
302 #define SVM_EXIT_WRITE_DR1 0x031
303 #define SVM_EXIT_WRITE_DR2 0x032
304 #define SVM_EXIT_WRITE_DR3 0x033
305 #define SVM_EXIT_WRITE_DR4 0x034
306 #define SVM_EXIT_WRITE_DR5 0x035
307 #define SVM_EXIT_WRITE_DR6 0x036
308 #define SVM_EXIT_WRITE_DR7 0x037
309 #define SVM_EXIT_EXCP_BASE 0x040
310 #define SVM_EXIT_INTR 0x060
311 #define SVM_EXIT_NMI 0x061
312 #define SVM_EXIT_SMI 0x062
313 #define SVM_EXIT_INIT 0x063
314 #define SVM_EXIT_VINTR 0x064
315 #define SVM_EXIT_CR0_SEL_WRITE 0x065
316 #define SVM_EXIT_IDTR_READ 0x066
317 #define SVM_EXIT_GDTR_READ 0x067
318 #define SVM_EXIT_LDTR_READ 0x068
319 #define SVM_EXIT_TR_READ 0x069
320 #define SVM_EXIT_IDTR_WRITE 0x06a
321 #define SVM_EXIT_GDTR_WRITE 0x06b
322 #define SVM_EXIT_LDTR_WRITE 0x06c
323 #define SVM_EXIT_TR_WRITE 0x06d
324 #define SVM_EXIT_RDTSC 0x06e
325 #define SVM_EXIT_RDPMC 0x06f
326 #define SVM_EXIT_PUSHF 0x070
327 #define SVM_EXIT_POPF 0x071
328 #define SVM_EXIT_CPUID 0x072
329 #define SVM_EXIT_RSM 0x073
330 #define SVM_EXIT_IRET 0x074
331 #define SVM_EXIT_SWINT 0x075
332 #define SVM_EXIT_INVD 0x076
333 #define SVM_EXIT_PAUSE 0x077
334 #define SVM_EXIT_HLT 0x078
335 #define SVM_EXIT_INVLPG 0x079
336 #define SVM_EXIT_INVLPGA 0x07a
337 #define SVM_EXIT_IOIO 0x07b
338 #define SVM_EXIT_MSR 0x07c
339 #define SVM_EXIT_TASK_SWITCH 0x07d
340 #define SVM_EXIT_FERR_FREEZE 0x07e
341 #define SVM_EXIT_SHUTDOWN 0x07f
342 #define SVM_EXIT_VMRUN 0x080
343 #define SVM_EXIT_VMMCALL 0x081
344 #define SVM_EXIT_VMLOAD 0x082
345 #define SVM_EXIT_VMSAVE 0x083
346 #define SVM_EXIT_STGI 0x084
347 #define SVM_EXIT_CLGI 0x085
348 #define SVM_EXIT_SKINIT 0x086
349 #define SVM_EXIT_RDTSCP 0x087
350 #define SVM_EXIT_ICEBP 0x088
351 #define SVM_EXIT_WBINVD 0x089
352 #define SVM_EXIT_MONITOR 0x08a
353 #define SVM_EXIT_MWAIT 0x08b
354 #define SVM_EXIT_MWAIT_COND 0x08c
355 #define SVM_EXIT_NPF 0x400
361 #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U
362 #define SVM_CR3_LONG_MBZ_MASK 0xfff0000000000000U
363 #define SVM_CR3_LONG_RESERVED_MASK 0x0000000000000fe7U
364 #define SVM_CR3_PAE_LEGACY_RESERVED_MASK 0x0000000000000007U
365 #define SVM_CR4_LEGACY_RESERVED_MASK 0xfe08e000U
366 #define SVM_CR4_RESERVED_MASK 0xfffffffffe08e000U
367 #define SVM_DR6_RESERVED_MASK 0xffffffffffff1ff0U
368 #define SVM_DR7_RESERVED_MASK 0xffffffff0000cc00U
369 #define SVM_EFER_RESERVED_MASK 0xffffffffffff0200U
373 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
456 "xchg %%rbx, regs+0x8\n\t" \
457 "xchg %%rcx, regs+0x10\n\t" \
458 "xchg %%rdx, regs+0x18\n\t" \
459 "xchg %%rbp, regs+0x28\n\t" \
460 "xchg %%rsi, regs+0x30\n\t" \
461 "xchg %%rdi, regs+0x38\n\t" \
462 "xchg %%r8, regs+0x40\n\t" \
463 "xchg %%r9, regs+0x48\n\t" \
464 "xchg %%r10, regs+0x50\n\t" \
465 "xchg %%r11, regs+0x58\n\t" \
466 "xchg %%r12, regs+0x60\n\t" \
467 "xchg %%r13, regs+0x68\n\t" \
468 "xchg %%r14, regs+0x70\n\t" \
469 "xchg %%r15, regs+0x78\n\t"
475 "mov regs+0x80, %%r15\n\t" \
476 "mov %%r15, 0x170(%%rax)\n\t" \
478 "mov %%r15, 0x1f8(%%rax)\n\t" \
483 "mov 0x170(%%rax), %%r15\n\t" \
484 "mov %%r15, regs+0x80\n\t" \
485 "mov 0x1f8(%%rax), %%r15\n\t" \