4 #include "x86/pmu.h"
195 	u32 global_ctl = pmu.msr_global_ctl;  in __precise_loop()
231 	if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) {  in adjust_events_range()
270 	if (!pmu.is_intel)  in is_gp()
279 	if (pmu.is_intel)  in event_to_global_idx()
280 		return cnt->ctr - (is_gp(cnt) ? pmu.msr_gp_counter_base :  in event_to_global_idx()
283 	if (pmu.msr_gp_counter_base == MSR_F15H_PERF_CTR0)  in event_to_global_idx()
284 		return (cnt->ctr - pmu.msr_gp_counter_base) / 2;  in event_to_global_idx()
286 		return cnt->ctr - pmu.msr_gp_counter_base;  in event_to_global_idx()
313 	wrmsr(pmu.msr_global_ctl, rdmsr(pmu.msr_global_ctl) | BIT_ULL(cnt->idx));  in global_enable()
321 	wrmsr(pmu.msr_global_ctl, rdmsr(pmu.msr_global_ctl) & ~BIT_ULL(cnt->idx));  in global_disable()
427 	for (i = 0; i < pmu.nr_gp_counters; i++) {  in check_gp_counter()
481 	for (i = 0, n = 0; n < pmu.nr_gp_counters; i++) {  in check_counters_many()
524 	int instruction_idx = pmu.is_intel ?  in check_counter_overflow()
541 	for (i = 0; i < pmu.nr_gp_counters + 1; i++) {  in check_counter_overflow()
547 			cnt.count &= (1ull << pmu.gp_counter_width) - 1;  in check_counter_overflow()
549 		if (i == pmu.nr_gp_counters) {  in check_counter_overflow()
550 			if (!pmu.is_intel)  in check_counter_overflow()
555 			cnt.count &= (1ull << pmu.gp_counter_width) - 1;  in check_counter_overflow()
566 		if (pmu.is_intel)  in check_counter_overflow()
574 		status = rdmsr(pmu.msr_global_status);  in check_counter_overflow()
576 		wrmsr(pmu.msr_global_status_clr, status);  in check_counter_overflow()
577 		status = rdmsr(pmu.msr_global_status);  in check_counter_overflow()
587 	int instruction_idx = pmu.is_intel ?  in check_gp_counter_cmask()
621 	for (i = 0; i < pmu.nr_gp_counters; i++) {  in check_rdpmc()
632 		if (pmu.msr_gp_counter_base == MSR_IA32_PERFCTR0)  in check_rdpmc()
638 		x &= (1ull << pmu.gp_counter_width) - 1;  in check_rdpmc()
650 		uint64_t x = val & ((1ull << pmu.fixed_counter_width) - 1);  in check_rdpmc()
673 	unsigned int instruction_idx = pmu.is_intel ?  in check_running_counter_wrmsr()
699 		count &= (1ull << pmu.gp_counter_width) - 1;  in check_running_counter_wrmsr()
707 		status = rdmsr(pmu.msr_global_status);  in check_running_counter_wrmsr()
718 	uint64_t gp_counter_width = (1ull << pmu.gp_counter_width) - 1;  in check_emulated_instr()
719 	unsigned int branch_idx = pmu.is_intel ?  in check_emulated_instr()
721 	unsigned int instruction_idx = pmu.is_intel ?  in check_emulated_instr()
750 		ecx = pmu.msr_global_ctl;  in check_emulated_instr()
777 		status = rdmsr(pmu.msr_global_status);  in check_emulated_instr()
796 	for (i = 0; i < pmu.nr_gp_counters; i++) {  in check_tsx_cycles()
865 	u64 val_max_width = val_64 & ((1ull << pmu.gp_counter_width) - 1);  in check_gp_counters_write_width()
872 	for (i = 0; i < pmu.nr_gp_counters; i++) {  in check_gp_counters_write_width()
890 	for (i = 0; i < pmu.nr_gp_counters; i++) {  in check_gp_counters_write_width()
921 	if (!pmu.nr_gp_counters || !pmu_arch_event_is_available(2))  in set_ref_cycle_expectations()
930 	 * costs for playing with the PMU MSRs on start and stop.  in set_ref_cycle_expectations()
973 		wrmsr(pmu.msr_global_ctl, 0);  in main()
977 	if (pmu.is_intel) {  in main()
978 		if (!pmu.version) {  in main()
979 			report_skip("No Intel Arch PMU is detected!");  in main()
1008 	printf("PMU version:         %d\n", pmu.version);  in main()
1009 	printf("GP counters:         %d\n", pmu.nr_gp_counters);  in main()
1010 	printf("GP counter width:    %d\n", pmu.gp_counter_width);  in main()
1011 	printf("Event Mask length:   %d\n", pmu.arch_event_mask_length);  in main()
1012 	printf("Arch Events (mask):  0x%x\n", pmu.arch_event_available);  in main()
1013 	printf("Fixed counters:      %d\n", pmu.nr_fixed_counters);  in main()
1014 	printf("Fixed counter width: %d\n", pmu.fixed_counter_width);  in main()
1016 	fixed_counters_num = MIN(pmu.nr_fixed_counters, ARRAY_SIZE(fixed_events));  in main()
1017 	if (pmu.nr_fixed_counters > ARRAY_SIZE(fixed_events))  in main()
1019 			    "Please update test case.", pmu.nr_fixed_counters,  in main()
1027 		pmu.msr_gp_counter_base = MSR_IA32_PMC0;  in main()
1035 	if (!pmu.is_intel) {  in main()
1037 		pmu.nr_gp_counters = AMD64_NUM_COUNTERS;  in main()
1038 		pmu.msr_gp_counter_base = MSR_K7_PERFCTR0;  in main()
1039 		pmu.msr_gp_event_select_base = MSR_K7_EVNTSEL0;  in main()