63 	 * and conversely setting those bits on 32-bit CPUs is not allowed.  Treat  in __test_msr_rw()
93 	       "Expected success on WRMSR(%s, 0x%llx), got vector %d",  in test_wrmsr()
102 	       "Expected #GP on WRMSR(%s, 0x%llx), got vector %d",  in test_wrmsr_fault()
112 	       "Expected #GP on RDMSR(%s), got vector %d", name, vector);  in test_rdmsr_fault()
121 	       "Expected #GP on emulated WRSMR(%s, 0x%llx), got vector %d",  in test_wrmsr_fep_fault()
132 		 * canonical checks on both Intel and AMD.  in test_msr()
185 		 * except on AMD-based systems with bit 18 set in MSR_K7_HWCR.  in test_mce_msrs()
188 		 * on bare metal).  in test_mce_msrs()
196 		 * The ADDR is a physical address, and all bits are writable on  in test_mce_msrs()
198 		 * enforce checks on bits 63:36 for 32-bit hosts.  The behavior  in test_mce_msrs()
199 		 * depends on the underlying hardware, e.g. a 32-bit guest on a  in test_mce_msrs()
212 	 * The theoretical maximum number of MCE banks is 32 (on Intel CPUs,  in test_mce_msrs()