41 	// read-only: 7, 11, 12
62 	 * Special case EFER since clearing LME/LMA is not allowed in 64-bit mode,  in __test_msr_rw()
63 	 * and conversely setting those bits on 32-bit CPUs is not allowed.  Treat  in __test_msr_rw()
78 		       (u32)(r >> 32), (u32)r, (u32)(val >> 32), (u32)val);  in __test_msr_rw()
127 	if (is_64bit_host || !msr->is_64bit_only) {  in test_msr()
128 		__test_msr_rw(msr->index, msr->name, msr->value, msr->keep);  in test_msr()
131 		 * The 64-bit only MSRs that take an address always perform  in test_msr()
134 		if (msr->is_64bit_only &&  in test_msr()
135 		    msr->value == addr_64)  in test_msr()
136 			test_wrmsr_fault(msr->index, msr->name, NONCANONICAL);  in test_msr()
138 		test_wrmsr_fault(msr->index, msr->name, msr->value);  in test_msr()
139 		test_rdmsr_fault(msr->index, msr->name);  in test_msr()
146 	char msr_name[32];  in test_custom_msr()
171 	char msr_name[32];  in test_mce_msrs()
178 		test_msr_rw(MSR_IA32_MCx_CTL(i), msr_name, -1ull);  in test_mce_msrs()
185 		 * except on AMD-based systems with bit 18 set in MSR_K7_HWCR.  in test_mce_msrs()
186 		 * That bit is not architectural and should not be set by  in test_mce_msrs()
194 		test_msr_rw(MSR_IA32_MCx_ADDR(i), msr_name, -1ull);  in test_mce_msrs()
197 		 * 64-bit hosts.  Don't test the negative case, as KVM doesn't  in test_mce_msrs()
198 		 * enforce checks on bits 63:36 for 32-bit hosts.  The behavior  in test_mce_msrs()
199 		 * depends on the underlying hardware, e.g. a 32-bit guest on a  in test_mce_msrs()
200 		 * 64-bit host may observe 64-bit values in the ADDR MSRs.  in test_mce_msrs()
207 		test_msr_rw(MSR_IA32_MCx_MISC(i), msr_name, -1ull);  in test_mce_msrs()
212 	 * The theoretical maximum number of MCE banks is 32 (on Intel CPUs,  in test_mce_msrs()
217 	for (i = nr_mce_banks; i < 32; i++) {  in test_mce_msrs()
240 	char msr_name[32];  in __test_x2apic_msrs()
258 		 * Except for ICR, the only 64-bit x2APIC register, bits 64:32  in __test_x2apic_msrs()
262 			test_wrmsr_fault(index, msr_name, -1ull);  in __test_x2apic_msrs()
264 		/* Bits 31:8 of self-IPI are reserved. */  in __test_x2apic_msrs()
266 			test_wrmsr_fault(index, "x2APIC Self-IPI", 0x100);  in __test_x2apic_msrs()
267 			test_wrmsr_fault(index, "x2APIC Self-IPI", 0xff00);  in __test_x2apic_msrs()
268 			test_wrmsr_fault(index, "x2APIC Self-IPI", 0xff000000ull);  in __test_x2apic_msrs()
272 			__test_msr_rw(index, msr_name, 0, -1ull);  in __test_x2apic_msrs()
276 			report(!(rdmsr(index) >> 32),  in __test_x2apic_msrs()
277 			       "Expected bits 63:32 == 0 for '%s'", msr_name);  in __test_x2apic_msrs()
326 	 * built-in testcases.  in main()