kvm-unit-tests/x86/la57.c

25 	 * directly read.  in get_test_register_value()
141 	 * TODO: A successful write to the MSR_GS_BASE corrupts it, and that  in test_register_write()
142 	 * breaks the wrmsr_safe macro (it uses GS for per-CPU data).  in test_register_write()
150 	       "Write to %s with value %lx did %s%s as expected",  in test_register_write()
157 	 * because it's not possible to read them directly.  in test_register_write()
165 		       "%s set to %lx as expected (actual value %lx)",  in test_register_write()
171 	 * Restore the old value directly without safety wrapper, to avoid test  in test_register_write()
172 	 * crashes related to temporary clobbered GDT/IDT/etc bases.  in test_register_write()
184 	/* 57-canonical value will work on CPUs that *support* LA57 */  in test_register()
217 	       "Tested invpcid type 0 with 0x%lx value - %s",  in __test_invpcid()
257 	 * only on Intel these instructions were extended to 64 bit.  in __test_canonical_checks()
260 	 * on Intel, to support cross-vendor migration.  This includes nested  in __test_canonical_checks()
264 	 * emulation.  Unfortunately, there is no foolproof way to detect bare  in __test_canonical_checks()
276 			    (is_intel() ? "due to known errata in KVM" : "due to AMD host"));  in __test_canonical_checks()
287 		report_skip("Skipping MSR_IA32_DS_AREA - PEBS not supported");  in __test_canonical_checks()
302 		report_skip("Skipping MSR_IA32_RTIT_ADDR* - Intel PT is not supported");  in __test_canonical_checks()
309 		report_skip("Skipping INVPCID - not supported");  in __test_canonical_checks()
329 	report(vector == expected, "%s when CR4.LA57 %ssupported (in %u-bit mode)",  in main()
341 		printf("Switching to 5 level paging mode and rerunning canonical tests.\n");  in main()