Lines Matching +full:32 +full:- +full:bit

14 	TEST_REGISTER_MSR /* upper 32 bits = msr address */
20 	u32 msr = test_register >> 32;  in get_test_register_value()
55 	u32 msr = test_register >> 32;  in set_test_register_value()
142 	 * breaks the wrmsr_safe macro (it uses GS for per-CPU data).  in test_register_write()
144 	if ((test_register >> 32) == MSR_GS_BASE && expect_success)  in test_register_write()
180 	/* Canonical 48 bit value should always succeed */  in test_register()
184 	/* 57-canonical value will work on CPUs that *support* LA57 */  in test_register()
199 		   ((u64)(address) << 32)), force_emulation)
217 	       "Tested invpcid type 0 with 0x%lx value - %s",  in __test_invpcid()
257 	 * only on Intel these instructions were extended to 64 bit.  in __test_canonical_checks()
260 	 * on Intel, to support cross-vendor migration.  This includes nested  in __test_canonical_checks()
287 		report_skip("Skipping MSR_IA32_DS_AREA - PEBS not supported");  in __test_canonical_checks()
302 		report_skip("Skipping MSR_IA32_RTIT_ADDR* - Intel PT is not supported");  in __test_canonical_checks()
309 		report_skip("Skipping INVPCID - not supported");  in __test_canonical_checks()
329 	report(vector == expected, "%s when CR4.LA57 %ssupported (in %u-bit mode)",  in main()
331 	       this_cpu_has(X86_FEATURE_LA57) ? "un" : "", is_64bit ? 64 : 32);  in main()