38 	db_addr[n] = regs->rip;  in handle_db()
42 		regs->rflags |= X86_EFLAGS_RF;  in handle_db()
45 		regs->rflags &= ~X86_EFLAGS_TF;  in handle_db()
74 	bp_addr = regs->rip;  in handle_bp()
140 	       "%sSingle-step #DB basic test", usermode);  in report_singlestep_basic()
148 	 * After being enabled, single-step breakpoints have a one instruction  in singlestep_basic()
177 	       "%sSingle-step #DB on emulated instructions", usermode);  in report_singlestep_emulated_instructions()
185 	 * Verify single-step #DB are generated correctly on emulated  in singlestep_emulated_instructions()
215 	       "%sSingle-step #DB w/ STI blocking", usermode);  in report_singlestep_with_sti_blocking()
224 	 * STI blocking doesn't suppress #DBs, thus the first single-step #DB  in singlestep_with_sti_blocking()
251 	       "%sSingle-step #DB w/ MOVSS blocking", usermode);  in report_singlestep_with_movss_blocking()
259 	 * MOVSS blocking suppresses single-step #DBs (and select other #DBs),  in singlestep_with_movss_blocking()
260 	 * thus the first single-step #DB should occur after MOVSS blocking  in singlestep_with_movss_blocking()
289 	       "%sSingle-Step + ICEBP #DB w/ MOVSS blocking", usermode);  in report_singlestep_with_movss_blocking_and_icebp()
298 	 * trap-like #DB, is intercepted if #DBs are intercepted, and manifests  in singlestep_with_movss_blocking_and_icebp()
299 	 * as a #DB VM-Exit, but the VM-Exit occurs on the ICEBP itself, i.e.  in singlestep_with_movss_blocking_and_icebp()
301 	 * correctly emulated as a trap-like #DB when intercepted, and that  in singlestep_with_movss_blocking_and_icebp()
302 	 * MOVSS blocking is handled correctly with respect to single-step  in singlestep_with_movss_blocking_and_icebp()
332 	       "Single-step #DB w/ MOVSS blocking and DR7.GD=1");  in report_singlestep_with_movss_blocking_and_dr7_gd()
343 	 * fault-like behavior.  Note, DR7.GD is cleared by the CPU upon  in singlestep_with_movss_blocking_and_dr7_gd()
345 	 * but the MOV DR6 below will be re-executed after handling the  in singlestep_with_movss_blocking_and_dr7_gd()
376 	       "%sSingle-step #DB w/ STI;HLT", usermode);  in report_singlestep_with_sti_hlt()
399 	 * STI blocking doesn't suppress #DBs, thus the first single-step #DB  in singlestep_with_sti_hlt()
467 	 * and is reserved if CR4.DE=1 (Debug Extensions enabled).  in main()
485 	report(bp_addr == (unsigned long)&sw_bp, "#BP");  in main()
488 	 * The CPU sets/clears bits 0-3 (trap bits for DR0-3) on #DB based on  in main()
489 	 * whether or not the corresponding DR0-3 got a match.  All other bits  in main()
492 	 * is reported correctly, and that DR6.BS is not set when single-step  in main()
526 	write_dr7(0x00d0040a); // 4-byte write  in main()
561 	write_dr7(0x00f0040a); // 4-byte read or write  in main()
592 	 * Here the #DB and #BP handlers are invoked once each.  in main()