78 extern struct pmu_caps pmu;
84 	if (pmu.msr_gp_counter_base == MSR_F15H_PERF_CTR0)  in MSR_GP_COUNTERx()
85 		return pmu.msr_gp_counter_base + 2 * i;  in MSR_GP_COUNTERx()
87 	return pmu.msr_gp_counter_base + i;  in MSR_GP_COUNTERx()
92 	if (pmu.msr_gp_event_select_base == MSR_F15H_PERF_CTL0)  in MSR_GP_EVENT_SELECTx()
93 		return pmu.msr_gp_event_select_base + 2 * i;  in MSR_GP_EVENT_SELECTx()
95 	return pmu.msr_gp_event_select_base + i;  in MSR_GP_EVENT_SELECTx()
100 	return !pmu.is_intel || !!pmu.version;  in this_cpu_has_pmu()
105 	return pmu.version > 1;  in this_cpu_has_perf_global_ctrl()
110 	return pmu.version > 1;  in this_cpu_has_perf_global_status()
115 	return pmu.arch_event_available & BIT(i);  in pmu_arch_event_is_available()
120 	return pmu.perf_cap & PMU_CAP_LBR_FMT;  in pmu_lbr_version()
125 	return pmu.perf_cap & PMU_CAP_FW_WRITES;  in pmu_has_full_writes()
130 	pmu.msr_gp_counter_base = MSR_IA32_PMC0;  in pmu_activate_full_writes()
135 	return pmu.msr_gp_counter_base == MSR_IA32_PMC0;  in pmu_use_full_writes()
147 	for (idx = 0; idx < pmu.nr_gp_counters; idx++) {  in pmu_reset_all_gp_counters()
157 	if (!pmu.nr_fixed_counters)  in pmu_reset_all_fixed_counters()
161 	for (idx = 0; idx < pmu.nr_fixed_counters; idx++)  in pmu_reset_all_fixed_counters()
173 	wrmsr(pmu.msr_global_status_clr, rdmsr(pmu.msr_global_status));  in pmu_clear_global_status()
178 	return pmu.version > 1;  in pmu_has_pebs()
183 	return (pmu.perf_cap & PERF_CAP_PEBS_FORMAT ) >> 8;  in pmu_pebs_format()
188 	return pmu.perf_cap & PMU_CAP_PEBS_BASELINE;  in pmu_has_pebs_baseline()