Lines Matching full:1

26 #define EFER_SCE		(1<<_EFER_SCE)
27 #define EFER_LME		(1<<_EFER_LME)
28 #define EFER_LMA		(1<<_EFER_LMA)
29 #define EFER_NX			(1<<_EFER_NX)
30 #define EFER_SVME		(1<<_EFER_SVME)
31 #define EFER_LMSLE		(1<<_EFER_LMSLE)
32 #define EFER_FFXSR		(1<<_EFER_FFXSR)
37 #define SPEC_CTRL_STIBP			BIT(1)
100 #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
101 #define DEBUGCTLMSR_BTF			(1UL <<  1) /* single-step on branches */
102 #define DEBUGCTLMSR_TR			(1UL <<  6)
103 #define DEBUGCTLMSR_BTS			(1UL <<  7)
104 #define DEBUGCTLMSR_BTINT		(1UL <<  8)
105 #define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
106 #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
107 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
130 #define CMCI_EN			(1ULL << 30)
140 #define RTIT_CTL_CYCLEACC		BIT(1)
203 #define FAM10H_MMIO_CONF_ENABLE		(1<<0)
302 #define FEATURE_CONTROL_LOCKED				(1<<0)
303 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
304 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
307 #define MSR_IA32_APICBASE_BSP		(1<<8)
308 #define MSR_IA32_APICBASE_ENABLE	(1<<11)
315 #define ARCH_CAP_RDCL_NO		(1ULL << 0)
316 #define ARCH_CAP_IBRS_ALL		(1ULL << 1)
317 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	(1ULL << 3)
318 #define ARCH_CAP_SSB_NO			(1ULL << 4)
319 #define ARCH_CAP_MDS_NO			(1ULL << 5)
320 #define ARCH_CAP_PSCHANGE_MC_NO		(1ULL << 6)
321 #define ARCH_CAP_TSX_CTRL_MSR		(1ULL << 7)
322 #define ARCH_CAP_TAA_NO			(1ULL << 8)
325 #define TSX_CTRL_RTM_DISABLE		(1ULL << 0)
326 #define TSX_CTRL_CPUID_CLEAR		(1ULL << 1)
337 #define THERM_INT_LOW_ENABLE		(1 << 0)
338 #define THERM_INT_HIGH_ENABLE		(1 << 1)
342 #define THERM_STATUS_PROCHOT		(1 << 0)
346 #define MSR_THERM2_CTL_TM_SELECT	(1ULL << 16)
353 #define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
354 #define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
355 #define MSR_IA32_MISC_ENABLE_EMON		(1ULL << 7)
356 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL	(1ULL << 11)
357 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL	(1ULL << 12)
358 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP	(1ULL << 16)
359 #define MSR_IA32_MISC_ENABLE_MWAIT		(1ULL << 18)
360 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID	(1ULL << 22)
361 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE	(1ULL << 23)
362 #define MSR_IA32_MISC_ENABLE_XD_DISABLE		(1ULL << 34)
365 #define MSR_IA32_MISC_ENABLE_X87_COMPAT		(1ULL << 2)
366 #define MSR_IA32_MISC_ENABLE_TM1		(1ULL << 3)
367 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE	(1ULL << 4)
368 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE	(1ULL << 6)
369 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK	(1ULL << 8)
370 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE	(1ULL << 9)
371 #define MSR_IA32_MISC_ENABLE_FERR		(1ULL << 10)
372 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX	(1ULL << 10)
373 #define MSR_IA32_MISC_ENABLE_TM2		(1ULL << 13)
374 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE	(1ULL << 19)
375 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK	(1ULL << 20)
376 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT	(1ULL << 24)
377 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE	(1ULL << 37)
378 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE	(1ULL << 38)
379 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE	(1ULL << 39)
518 #define MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI		(1ULL << 8)
519 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS	(1ULL << 29)
532 #define SEV_STATUS_SEV_ES_ENABLED	BIT(1)