Lines Matching +full:0 +full:x80
26 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
33 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
34 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
35 #define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */
36 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
37 #define DMAR_ECAP_REG_HI 0X14
38 #define DMAR_GCMD_REG 0x18 /* Global command */
39 #define DMAR_GSTS_REG 0x1c /* Global status */
40 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
41 #define DMAR_RTADDR_REG_HI 0X24
42 #define DMAR_CCMD_REG 0x28 /* Context command */
43 #define DMAR_CCMD_REG_HI 0x2c
44 #define DMAR_FSTS_REG 0x34 /* Fault status */
45 #define DMAR_FECTL_REG 0x38 /* Fault control */
46 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data */
47 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr */
48 #define DMAR_FEUADDR_REG 0x44 /* Upper address */
49 #define DMAR_AFLOG_REG 0x58 /* Advanced fault control */
50 #define DMAR_AFLOG_REG_HI 0X5c
51 #define DMAR_PMEN_REG 0x64 /* Enable protected memory region */
52 #define DMAR_PLMBASE_REG 0x68 /* PMRR low addr */
53 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
54 #define DMAR_PHMBASE_REG 0x70 /* PMRR high base addr */
55 #define DMAR_PHMBASE_REG_HI 0X74
56 #define DMAR_PHMLIMIT_REG 0x78 /* PMRR high limit */
57 #define DMAR_PHMLIMIT_REG_HI 0x7c
58 #define DMAR_IQH_REG 0x80 /* Invalidation queue head */
59 #define DMAR_IQH_REG_HI 0X84
60 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail */
61 #define DMAR_IQT_REG_HI 0X8c
62 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr */
63 #define DMAR_IQA_REG_HI 0x94
64 #define DMAR_ICS_REG 0x9c /* Invalidation complete status */
65 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr */
66 #define DMAR_IRTA_REG_HI 0xbc
67 #define DMAR_IECTL_REG 0xa0 /* Invalidation event control */
68 #define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */
69 #define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */
70 #define DMAR_IEUADDR_REG 0xac /* Invalidation event address */
71 #define DMAR_PQH_REG 0xc0 /* Page request queue head */
72 #define DMAR_PQH_REG_HI 0xc4
73 #define DMAR_PQT_REG 0xc8 /* Page request queue tail*/
74 #define DMAR_PQT_REG_HI 0xcc
75 #define DMAR_PQA_REG 0xd0 /* Page request queue address */
76 #define DMAR_PQA_REG_HI 0xd4
77 #define DMAR_PRS_REG 0xdc /* Page request status */
78 #define DMAR_PECTL_REG 0xe0 /* Page request event control */
79 #define DMAR_PEDATA_REG 0xe4 /* Page request event data */
80 #define DMAR_PEADDR_REG 0xe8 /* Page request event address */
81 #define DMAR_PEUADDR_REG 0xec /* Page event upper address */
82 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability */
83 #define DMAR_MTRRCAP_REG_HI 0x104
84 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type */
85 #define DMAR_MTRRDEF_REG_HI 0x10c
87 #define VTD_GCMD_IR_TABLE 0x1000000
88 #define VTD_GCMD_IR 0x2000000
89 #define VTD_GCMD_QI 0x4000000
90 #define VTD_GCMD_WBF 0x8000000 /* Write Buffer Flush */
91 #define VTD_GCMD_SFL 0x20000000 /* Set Fault Log */
92 #define VTD_GCMD_ROOT 0x40000000
93 #define VTD_GCMD_DMAR 0x80000000
100 #define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT)
102 #define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
108 #define VTD_CONTEXT_TT_MULTI_LEVEL 0
112 #define VTD_PTE_R (1 << 0)