Lines Matching +full:0 +full:x0
10 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
17 #define APIC_ID 0x20
19 #define APIC_LVR 0x30
20 #define APIC_LVR_MASK 0xFF00FF
21 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
22 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
24 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
28 #define APIC_XAPIC(x) ((x) >= 0x14)
29 #define APIC_TASKPRI 0x80
30 #define APIC_TPRI_MASK 0xFFu
31 #define APIC_ARBPRI 0x90
32 #define APIC_ARBPRI_MASK 0xFFu
33 #define APIC_PROCPRI 0xA0
34 #define APIC_EOI 0xB0
35 #define APIC_EIO_ACK 0x0
36 #define APIC_RRR 0xC0
37 #define APIC_LDR 0xD0
38 #define APIC_LDR_MASK (0xFFu << 24)
39 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
41 #define APIC_ALL_CPUS 0xFFu
42 #define APIC_DFR 0xE0
43 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
44 #define APIC_DFR_FLAT 0xFFFFFFFFul
45 #define APIC_SPIV 0xF0
48 #define APIC_ISR 0x100
49 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
50 #define APIC_TMR 0x180
51 #define APIC_IRR 0x200
52 #define APIC_ESR 0x280
53 #define APIC_ESR_SEND_CS 0x00001
54 #define APIC_ESR_RECV_CS 0x00002
55 #define APIC_ESR_SEND_ACC 0x00004
56 #define APIC_ESR_RECV_ACC 0x00008
57 #define APIC_ESR_SENDILL 0x00020
58 #define APIC_ESR_RECVILL 0x00040
59 #define APIC_ESR_ILLREGA 0x00080
60 #define APIC_CMCI 0x2F0
61 #define APIC_ICR 0x300
62 #define APIC_DEST_SELF 0x40000
63 #define APIC_DEST_ALLINC 0x80000
64 #define APIC_DEST_ALLBUT 0xC0000
65 #define APIC_ICR_RR_MASK 0x30000
66 #define APIC_ICR_RR_INVALID 0x00000
67 #define APIC_ICR_RR_INPROG 0x10000
68 #define APIC_ICR_RR_VALID 0x20000
69 #define APIC_INT_LEVELTRIG 0x08000
70 #define APIC_INT_ASSERT 0x04000
71 #define APIC_ICR_BUSY 0x01000
72 #define APIC_DEST_LOGICAL 0x00800
73 #define APIC_DEST_PHYSICAL 0x00000
74 #define APIC_DM_FIXED 0x00000
75 #define APIC_DM_LOWEST 0x00100
76 #define APIC_DM_SMI 0x00200
77 #define APIC_DM_REMRD 0x00300
78 #define APIC_DM_NMI 0x00400
79 #define APIC_DM_INIT 0x00500
80 #define APIC_DM_STARTUP 0x00600
81 #define APIC_DM_EXTINT 0x00700
82 #define APIC_VECTOR_MASK 0x000FF
83 #define APIC_ICR2 0x310
84 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
86 #define APIC_LVTT 0x320
87 #define APIC_LVTTHMR 0x330
88 #define APIC_LVTPC 0x340
89 #define APIC_LVT0 0x350
90 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
91 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
93 #define APIC_TIMER_BASE_CLKIN 0x0
94 #define APIC_TIMER_BASE_TMBASE 0x1
95 #define APIC_TIMER_BASE_DIV 0x2
97 #define APIC_LVT_TIMER_ONESHOT (0 << 17)
105 #define APIC_MODE_MASK 0x700
106 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
107 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8))
108 #define APIC_MODE_FIXED 0x0
109 #define APIC_MODE_NMI 0x4
110 #define APIC_MODE_EXTINT 0x7
111 #define APIC_LVT1 0x360
112 #define APIC_LVTERR 0x370
113 #define APIC_TMICT 0x380
114 #define APIC_TMCCT 0x390
115 #define APIC_TDCR 0x3E0
116 #define APIC_SELF_IPI 0x3F0
118 #define APIC_TDR_DIV_1 0xB
119 #define APIC_TDR_DIV_2 0x0
120 #define APIC_TDR_DIV_4 0x1
121 #define APIC_TDR_DIV_8 0x2
122 #define APIC_TDR_DIV_16 0x3
123 #define APIC_TDR_DIV_32 0x8
124 #define APIC_TDR_DIV_64 0x9
125 #define APIC_TDR_DIV_128 0xA
126 #define APIC_EILVT0 0x500
129 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
130 #define APIC_EILVT_MSG_FIX 0x0
131 #define APIC_EILVT_MSG_SMI 0x2
132 #define APIC_EILVT_MSG_NMI 0x4
133 #define APIC_EILVT_MSG_EXT 0x7
135 #define APIC_EILVT1 0x510
136 #define APIC_EILVT2 0x520
137 #define APIC_EILVT3 0x530
139 #define APIC_BASE_MSR 0x800