18 	/* FPRs 0, 2, 4, 6 */
31 	/* GRs 0 and 1 */
88 	AS_PRIM = 0,
94 #define PSW_MASK_DAT			0x0400000000000000UL
95 #define PSW_MASK_HOME			0x0000C00000000000UL
96 #define PSW_MASK_IO			0x0200000000000000UL
97 #define PSW_MASK_EXT			0x0100000000000000UL
98 #define PSW_MASK_KEY			0x00F0000000000000UL
99 #define PSW_MASK_WAIT			0x0002000000000000UL
100 #define PSW_MASK_PSTATE			0x0001000000000000UL
101 #define PSW_MASK_EA			0x0000000100000000UL
102 #define PSW_MASK_BA			0x0000000080000000UL
118 #define CR0_EXTM_MASK			0x0000000000006200UL /* Combined external masks */
124 	uint8_t		pad_0x0000[0x0080 - 0x0000];	/* 0x0000 */
125 	uint32_t	ext_int_param;			/* 0x0080 */
126 	uint16_t	cpu_addr;			/* 0x0084 */
127 	uint16_t	ext_int_code;			/* 0x0086 */
128 	uint16_t	svc_int_id;			/* 0x0088 */
129 	uint16_t	svc_int_code;			/* 0x008a */
130 	uint16_t	pgm_int_id;			/* 0x008c */
131 	uint16_t	pgm_int_code;			/* 0x008e */
132 	uint32_t	dxc_vxc;			/* 0x0090 */
133 	uint16_t	mon_class_nb;			/* 0x0094 */
134 	uint8_t		per_code;			/* 0x0096 */
135 	uint8_t		per_atmid;			/* 0x0097 */
136 	uint64_t	per_addr;			/* 0x0098 */
137 	uint8_t		exc_acc_id;			/* 0x00a0 */
138 	uint8_t		per_acc_id;			/* 0x00a1 */
139 	uint8_t		op_acc_id;			/* 0x00a2 */
140 	uint8_t		arch_mode_id;			/* 0x00a3 */
141 	uint8_t		pad_0x00a4[0x00a8 - 0x00a4];	/* 0x00a4 */
142 	uint64_t	trans_exc_id;			/* 0x00a8 */
143 	uint64_t	mon_code;			/* 0x00b0 */
144 	uint32_t	subsys_id_word;			/* 0x00b8 */
145 	uint32_t	io_int_param;			/* 0x00bc */
146 	uint32_t	io_int_word;			/* 0x00c0 */
147 	uint8_t		pad_0x00c4[0x00c8 - 0x00c4];	/* 0x00c4 */
148 	uint32_t	stfl;				/* 0x00c8 */
149 	uint8_t		pad_0x00cc[0x00e8 - 0x00cc];	/* 0x00cc */
150 	uint64_t	mcck_int_code;			/* 0x00e8 */
151 	uint8_t		pad_0x00f0[0x00f4 - 0x00f0];	/* 0x00f0 */
152 	uint32_t	ext_damage_code;		/* 0x00f4 */
153 	uint64_t	failing_storage_addr;		/* 0x00f8 */
154 	uint64_t	emon_ca_origin;			/* 0x0100 */
155 	uint32_t	emon_ca_size;			/* 0x0108 */
156 	uint32_t	emon_exc_count;			/* 0x010c */
157 	uint64_t	breaking_event_addr;		/* 0x0110 */
158 	uint8_t		pad_0x0118[0x0120 - 0x0118];	/* 0x0118 */
159 	struct psw	restart_old_psw;		/* 0x0120 */
160 	struct psw	ext_old_psw;			/* 0x0130 */
161 	struct psw	svc_old_psw;			/* 0x0140 */
162 	struct psw	pgm_old_psw;			/* 0x0150 */
163 	struct psw	mcck_old_psw;			/* 0x0160 */
164 	struct psw	io_old_psw;			/* 0x0170 */
165 	uint8_t		pad_0x0180[0x01a0 - 0x0180];	/* 0x0180 */
166 	struct psw	restart_new_psw;		/* 0x01a0 */
167 	struct psw	ext_new_psw;			/* 0x01b0 */
168 	struct psw	svc_new_psw;			/* 0x01c0 */
169 	struct psw	pgm_new_psw;			/* 0x01d0 */
170 	struct psw	mcck_new_psw;			/* 0x01e0 */
171 	struct psw	io_new_psw;			/* 0x01f0 */
173 	uint64_t	sw_int_grs[16];			/* 0x0200 */
174 	uint8_t		pad_0x0280[0x0308 - 0x0280];	/* 0x0280 */
175 	uint64_t	sw_int_crs[16];			/* 0x0308 */
176 	struct psw	sw_int_psw;			/* 0x0388 */
177 	struct cpu	*this_cpu;			/* 0x0398 */
178 	uint8_t		pad_0x03a0[0x11b0 - 0x03a0];	/* 0x03a0 */
179 	uint64_t	mcck_ext_sa_addr;		/* 0x11b0 */
180 	uint8_t		pad_0x11b8[0x1200 - 0x11b8];	/* 0x11b8 */
181 	uint64_t	fprs_sa[16];			/* 0x1200 */
182 	uint64_t	grs_sa[16];			/* 0x1280 */
183 	struct psw	psw_sa;				/* 0x1300 */
184 	uint8_t		pad_0x1310[0x1318 - 0x1310];	/* 0x1310 */
185 	uint32_t	prefix_sa;			/* 0x1318 */
186 	uint32_t	fpc_sa;				/* 0x131c */
187 	uint8_t		pad_0x1320[0x1324 - 0x1320];	/* 0x1320 */
188 	uint32_t	tod_pr_sa;			/* 0x1324 */
189 	uint64_t	cputm_sa;			/* 0x1328 */
190 	uint64_t	cc_sa;				/* 0x1330 */
191 	uint8_t		pad_0x1338[0x1340 - 0x1338];	/* 0x1338 */
192 	uint32_t	ars_sa[16];			/* 0x1340 */
193 	uint64_t	crs_sa[16];			/* 0x1380 */
194 	uint8_t		pad_0x1400[0x1800 - 0x1400];	/* 0x1400 */
195 	uint8_t		pgm_int_tdb[0x1900 - 0x1800];	/* 0x1800 */
197 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size");
203 #define PGM_INT_CODE_OPERATION			0x01
204 #define PGM_INT_CODE_PRIVILEGED_OPERATION	0x02
205 #define PGM_INT_CODE_EXECUTE			0x03
206 #define PGM_INT_CODE_PROTECTION			0x04
207 #define PGM_INT_CODE_ADDRESSING			0x05
208 #define PGM_INT_CODE_SPECIFICATION		0x06
209 #define PGM_INT_CODE_DATA			0x07
210 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW	0x08
211 #define PGM_INT_CODE_FIXED_POINT_DIVIDE		0x09
212 #define PGM_INT_CODE_DECIMAL_OVERFLOW		0x0a
213 #define PGM_INT_CODE_DECIMAL_DIVIDE		0x0b
214 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW	0x0c
215 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW	0x0d
216 #define PGM_INT_CODE_HFP_SIGNIFICANCE		0x0e
217 #define PGM_INT_CODE_HFP_DIVIDE			0x0f
218 #define PGM_INT_CODE_SEGMENT_TRANSLATION	0x10
219 #define PGM_INT_CODE_PAGE_TRANSLATION		0x11
220 #define PGM_INT_CODE_TRANSLATION_SPEC		0x12
221 #define PGM_INT_CODE_SPECIAL_OPERATION		0x13
222 #define PGM_INT_CODE_OPERAND			0x15
223 #define PGM_INT_CODE_TRACE_TABLE		0x16
224 #define PGM_INT_CODE_VECTOR_PROCESSING		0x1b
225 #define PGM_INT_CODE_SPACE_SWITCH_EVENT		0x1c
226 #define PGM_INT_CODE_HFP_SQUARE_ROOT		0x1d
227 #define PGM_INT_CODE_PC_TRANSLATION_SPEC	0x1f
228 #define PGM_INT_CODE_AFX_TRANSLATION		0x20
229 #define PGM_INT_CODE_ASX_TRANSLATION		0x21
230 #define PGM_INT_CODE_LX_TRANSLATION		0x22
231 #define PGM_INT_CODE_EX_TRANSLATION		0x23
232 #define PGM_INT_CODE_PRIMARY_AUTHORITY		0x24
233 #define PGM_INT_CODE_SECONDARY_AUTHORITY	0x25
234 #define PGM_INT_CODE_LFX_TRANSLATION		0x26
235 #define PGM_INT_CODE_LSX_TRANSLATION		0x27
236 #define PGM_INT_CODE_ALET_SPECIFICATION		0x28
237 #define PGM_INT_CODE_ALEN_TRANSLATION		0x29
238 #define PGM_INT_CODE_ALE_SEQUENCE		0x2a
239 #define PGM_INT_CODE_ASTE_VALIDITY		0x2b
240 #define PGM_INT_CODE_ASTE_SEQUENCE		0x2c
241 #define PGM_INT_CODE_EXTENDED_AUTHORITY		0x2d
242 #define PGM_INT_CODE_LSTE_SEQUENCE		0x2e
243 #define PGM_INT_CODE_ASTE_INSTANCE		0x2f
244 #define PGM_INT_CODE_STACK_FULL			0x30
245 #define PGM_INT_CODE_STACK_EMPTY		0x31
246 #define PGM_INT_CODE_STACK_SPECIFICATION	0x32
247 #define PGM_INT_CODE_STACK_TYPE			0x33
248 #define PGM_INT_CODE_STACK_OPERATION		0x34
249 #define PGM_INT_CODE_ASCE_TYPE			0x38
250 #define PGM_INT_CODE_REGION_FIRST_TRANS		0x39
251 #define PGM_INT_CODE_REGION_SECOND_TRANS	0x3a
252 #define PGM_INT_CODE_REGION_THIRD_TRANS		0x3b
253 #define PGM_INT_CODE_SECURE_STOR_ACCESS		0x3d
254 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS	0x3e
255 #define PGM_INT_CODE_SECURE_STOR_VIOLATION	0x3f
256 #define PGM_INT_CODE_MONITOR_EVENT		0x40
257 #define PGM_INT_CODE_PER			0x80
258 #define PGM_INT_CODE_CRYPTO_OPERATION		0x119
259 #define PGM_INT_CODE_TX_ABORTED_EVENT		0x200
275 	asm volatile("stap %0" : "=Q" (cpu_address));  in stap()
283 	asm volatile("stidp %0" : "=Q" (cpuid));  in stidp()
289 	TPROT_READ_WRITE = 0,
300 		"	tprot	0(%1),0(%2)\n"  in tprot()
301 		"	ipm	%0\n"  in tprot()
302 		"	srl	%0,28\n"  in tprot()
310 		"	lctlg	%1,%1,%0\n"  in lctlg()
319 		"	stctg	%1,%1,%0\n"  in stctg()
344 	uint32_t mask_upper = 0, mask_lower = 0;  in extract_psw_mask()
347 		"	epsw	%0,%1\n"  in extract_psw_mask()
359 		.addr = 0,  in load_psw_mask()
361 	uint64_t tmp = 0;  in load_psw_mask()
364 		"	larl	%0,0f\n"  in load_psw_mask()
365 		"	stg	%0,8(%1)\n"  in load_psw_mask()
366 		"	lpswe	0(%1)\n"  in load_psw_mask()
367 		"0:\n"  in load_psw_mask()
378 	asm volatile("  lpswe 0(%0)\n" : : "a" (&psw) : "memory", "cc");  in disabled_wait()
447 	asm volatile("	svc %0\n" : : "i" (SVC_LEAVE_PSTATE));  in leave_pstate()
452 	register int r0 asm("0") = (fc << 28) | sel1;  in stsi()
457 		"stsi	0(%3)\n"  in stsi()
468 	register unsigned long r0 asm("0") = 0;  in stsi_get_fc()
469 	register unsigned long r1 asm("1") = 0;  in stsi_get_fc()
472 	asm volatile("stsi	0\n"  in stsi_get_fc()
487 		"       .insn   rre,0xb2200000,%1,%2\n"  /* servc %1,%2 */  in servc()
488 		"       ipm     %0\n"  in servc()
489 		"       srl     %0,28"  in servc()
497 	asm volatile("	spx %0" : : "Q" (new_prefix) : "memory");  in set_prefix()
504 	asm volatile("	stpx %0" : "=Q" (current_prefix));  in get_prefix()
510 	asm volatile("diag	0,0,0x44\n");  in diag44()
517 		"diag	0,0,0x500\n"  in diag500()