Lines Matching +full:psci +full:- +full:0

2  * ARM Power State and Coordination Interface (PSCI) header
4  * This header holds common PSCI defines and macros shared
15  * PSCI v0.1 interface
17  * The PSCI v0.1 function numbers are implementation defined.
19  * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
21  * to PSCI v0.1.
24 /* PSCI v0.2 interface */
25 #define PSCI_0_2_FN_BASE			0x84000000
27 #define PSCI_0_2_64BIT				0x40000000
32 #define PSCI_0_2_FN_PSCI_VERSION		PSCI_0_2_FN(0)
54 /* PSCI v0.2 power state encoding for CPU_SUSPEND function */
55 #define PSCI_0_2_POWER_STATE_ID_MASK		0xffff
56 #define PSCI_0_2_POWER_STATE_ID_SHIFT		0
59 				(0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
62 				(0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
64 /* PSCI extended power state encoding for CPU_SUSPEND function */
65 #define PSCI_1_0_EXT_POWER_STATE_ID_MASK	0xfffffff
66 #define PSCI_1_0_EXT_POWER_STATE_ID_SHIFT	0
69 				(0x1 << PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT)
71 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
72 #define PSCI_0_2_AFFINITY_LEVEL_ON		0
76 /* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
77 #define PSCI_0_2_TOS_UP_MIGRATE			0
81 /* PSCI version decoding (independent of PSCI version) */
84 		((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
91 /* PSCI features decoding (>=1.0) */
94 			(0x1 << PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT)
96 /* PSCI return values (inclusive of all PSCI versions) */
97 #define PSCI_RET_SUCCESS			0
98 #define PSCI_RET_NOT_SUPPORTED			-1
99 #define PSCI_RET_INVALID_PARAMS			-2
100 #define PSCI_RET_DENIED				-3
101 #define PSCI_RET_ALREADY_ON			-4
102 #define PSCI_RET_ON_PENDING			-5
103 #define PSCI_RET_INTERNAL_FAILURE		-6
104 #define PSCI_RET_NOT_PRESENT			-7
105 #define PSCI_RET_DISABLED			-8
106 #define PSCI_RET_INVALID_ADDRESS		-9