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6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * http://www.pcisig.com/ for how to get them):
13 * PCI to PCI Bridge Specification
36 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
42 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
50 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
76 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
82 * 0xffffffff to the register, and reading it back. Only
113 /* 0x35-0x3b are reserved */
119 /* Header type 1 (PCI-to-PCI bridges) */
147 /* 0x35-0x3b is reserved */
149 /* 0x3c-0x3d are same as for htype 0 */
180 /* 0x3c-0x3d are same as for htype 0 */
182 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
188 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
194 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
195 /* 0x48-0x7f reserved */
206 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
208 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
211 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
213 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
216 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
244 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
245 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
261 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
263 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
272 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
281 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
284 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
300 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
301 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
305 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
306 #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
307 #define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */
308 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
309 #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
310 #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
312 /* MSI-X registers */
316 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
326 /* MSI-X Table entry format */
342 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
343 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
365 /* 0-5 map to BARs 0-5 respectively */
371 /* 9-14 map to VF BARs 0-5 respectively */
374 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
377 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
381 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
382 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
385 /* 0x08-0xfc reserved */
394 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
397 /* PCI-X registers (Type 0 (non-bridge) devices) */
402 #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
403 #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
404 #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
405 #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
406 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
418 #define PCI_X_STATUS 4 /* PCI-X capabilities */
421 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
426 #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
428 #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
437 /* PCI-X registers (Type 1 (bridge) devices) */
443 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
465 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
466 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
480 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
486 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
503 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
525 #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
557 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
558 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
570 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
596 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
610 * Use pcie_capability_read_word() and similar interfaces to use them
614 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
618 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
621 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
641 /* Extended Capabilities (PCI-X 2.0 and Express) */
653 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
656 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
657 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
707 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
722 /* Non-fatal Err Reporting Enable */
735 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
784 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
785 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */
795 * want to use these directly, just use pci_find_ht_capability() and it
809 #define HT_MSI_FLAGS 0x02 /* Offset to flags */
813 #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */
815 #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */
824 /* Alternative Routing-ID Interpretation */
868 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
871 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
877 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
919 #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */
924 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
936 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
944 #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */