Lines Matching full:control
182 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
210 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
243 #define PCI_PM_CTRL 4 /* PM control and status register */
252 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
268 #define PCI_AGP_COMMAND 8 /* Control register */
296 #define PCI_MSI_FLAGS 2 /* Message Control */
313 #define PCI_MSIX_FLAGS 2 /* Message Control */
336 #define PCI_CHSWP_CSR 2 /* Control and Status Register */
432 #define PCI_X_ECC_CSR 8 /* ECC control and status */
484 #define PCI_EXP_DEVCTL 8 /* Device Control */
521 #define PCI_EXP_LNKCTL 16 /* Link Control */
522 #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
564 #define PCI_EXP_SLTCTL 24 /* Slot Control */
571 #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
575 #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */
579 #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */
582 #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
594 #define PCI_EXP_RTCTL 28 /* Root Control */
606 * The Device Capabilities 2, Device Status 2, Device Control 2,
607 * Link Capabilities 2, Link Status 2, Link Control 2,
608 * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
619 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
635 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
638 #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
651 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
658 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
684 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
829 #define PCI_ARI_CTRL 0x06 /* ARI Control Register */
839 #define PCI_ATS_CTRL 0x06 /* ATS Control Register */
846 #define PCI_PRI_CTRL 0x04 /* PRI control register */
861 #define PCI_PASID_CTRL 0x06 /* PASID control register */
871 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
906 /* Access Control Service */
913 #define PCI_ACS_EC 0x20 /* P2P Egress Control */
915 #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
916 #define PCI_ACS_CTRL 0x06 /* ACS Control Register */
917 #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
930 #define PCI_REBAR_CTRL 8 /* control register */