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62 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
67 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
68 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
69 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
74 #define PCI_BIST 0x0f /* 8 bits */
114 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
115 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
116 #define PCI_MIN_GNT 0x3e /* 8 bits */
117 #define PCI_MAX_LAT 0x3f /* 8 bits */
254 #define PCI_PM_SIZEOF 8
268 #define PCI_AGP_COMMAND 8 /* Control register */
285 #define PCI_CAP_VPD_SIZEOF 8
304 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
305 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
320 #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */
330 #define PCI_MSIX_ENTRY_DATA 8
362 #define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
370 #define PCI_EA_BEI_ROM 8 /* Expansion ROM */
392 #define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */
412 #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */
432 #define PCI_X_ECC_CSR 8 /* ECC control and status */
433 #define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */
484 #define PCI_EXP_DEVCTL 8 /* Device Control */
697 #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
744 #define PCI_VC_PORT_CAP2 8
773 #define PCI_PWR_DATA 8 /* Data Register */
775 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
828 #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
833 #define PCI_EXT_CAP_ARI_SIZEOF 8
843 #define PCI_EXT_CAP_ATS_SIZEOF 8
865 #define PCI_EXT_CAP_PASID_SIZEOF 8
904 #define PCI_EXT_CAP_LTR_SIZEOF 8
926 #define PCI_SATA_SIZEOF_SHORT 8
930 #define PCI_REBAR_CTRL 8 /* control register */