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277 #define PCI_AGP_SIZEOF 12
306 #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
308 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
324 #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
331 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
413 #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */
417 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
508 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
675 #define PCI_EXT_CAP_DSN_SIZEOF 12
699 #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
749 #define PCI_VC_PORT_CTRL 12
780 #define PCI_PWR_CAP 12 /* Capability */
842 #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
947 #define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */