Lines Matching +full:0 +full:x0
17 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
23 .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt)
27 .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt)
35 asm volatile("mrs %0, " xstr(r) : "=r" (__val)); \
41 asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val)); \
42 } while (0)
46 asm volatile("mrs_s %0, " xstr(r) : "=r" (__val)); \
52 asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\
53 } while (0)
62 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
68 " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
72 " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
80 #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
81 #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
82 #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
83 #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
84 #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
86 #define TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
87 #define TFSR_EL1_TF0 _BITULL(0)
108 #define SCTLR_EL1_M _BITULL(0)
122 #define ZCR_EL1_LEN GENMASK(3, 0)