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12 #define CR_M	(1 << 0)	/* MMU enable				*/
13 #define CR_A	(1 << 1)	/* Alignment abort enable		*/
14 #define CR_C	(1 << 2)	/* Dcache enable			*/
15 #define CR_W	(1 << 3)	/* Write buffer enable			*/
16 #define CR_P	(1 << 4)	/* 32-bit exception handler		*/
17 #define CR_D	(1 << 5)	/* 32-bit data address range		*/
18 #define CR_L	(1 << 6)	/* Implementation defined		*/
19 #define CR_B	(1 << 7)	/* Big endian				*/
20 #define CR_S	(1 << 8)	/* System MMU protection		*/
21 #define CR_R	(1 << 9)	/* ROM MMU protection			*/
22 #define CR_F	(1 << 10)	/* Implementation defined		*/
23 #define CR_Z	(1 << 11)	/* Implementation defined		*/
24 #define CR_I	(1 << 12)	/* Icache enable			*/
25 #define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
26 #define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
27 #define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
28 #define CR_DT	(1 << 16)
29 #define CR_HA	(1 << 17)	/* Hardware management of Access Flag	*/
30 #define CR_IT	(1 << 18)
31 #define CR_ST	(1 << 19)
32 #define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
33 #define CR_U	(1 << 22)	/* Unaligned access operation		*/
34 #define CR_XP	(1 << 23)	/* Extended page tables			*/
35 #define CR_VE	(1 << 24)	/* Vectored interrupts			*/
36 #define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
37 #define CR_TRE	(1 << 28)	/* TEX remap enable			*/
38 #define CR_AFE	(1 << 29)	/* Access flag enable			*/
39 #define CR_TE	(1 << 30)	/* Thumb exception enable		*/