Lines Matching +full:pmu +full:- +full:sw +full:- +full:incr
2 * Test the ARM Performance Monitors Unit (PMU).
4 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
43 /* Some PMU events */
75 #define PRE_OVERFLOW2_32 (ALL_SET_32 - COUNT - MARGIN)
76 #define PRE_OVERFLOW2_64 (ALL_SET_64 - COUNT - MARGIN)
86 struct pmu { struct
98 static struct pmu pmu; variable
176 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); in pmu_reset()
260 * The low 32-bits of PMCEID0/1 respectively describe in is_event_supported()
261 * event support for events 0-31/32-63. Their High in is_event_supported()
262 * 32-bits describe support for extended events in is_event_supported()
284 if (!pmu.nb_implemented_counters) { in test_event_introspection()
295 if (pmu.version >= ID_DFR0_PMU_V3_8_1) { in test_event_introspection()
373 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); in pmu_reset()
388 if (!pmu.nb_implemented_counters) { in test_event_counter_config()
432 if (pmu.nb_implemented_counters < nb_events) { in satisfy_prerequisites()
434 pmu.nb_implemented_counters); in satisfy_prerequisites()
451 * Bits [63:0] are always incremented for 64-bit counters, in pmevcntr_mask()
452 * even if the PMU is configured to generate an overflow at in pmevcntr_mask()
456 * pseudo-code in the ARM ARM DDI 0487I.a, section J1.1.1. in pmevcntr_mask()
458 if (pmu.version >= ID_DFR0_PMU_V3_8_5) in pmevcntr_mask()
466 if (overflow_at_64bits && pmu.version < ID_DFR0_PMU_V3_8_5) { in check_overflow_prerequisites()
486 implemented_counter_mask = BIT(pmu.nb_implemented_counters) - 1; in test_basic_event_count()
502 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P | pmcr_lp); in test_basic_event_count()
504 report(get_pmcr() == (pmu.pmcr_ro | PMU_PMCR_LC | pmcr_lp), "pmcr: reset counters"); in test_basic_event_count()
509 "counter #0 preset to pre-overflow value"); in test_basic_event_count()
545 precise_instrs_loop(20, pmu.pmcr_ro | PMU_PMCR_E); in test_basic_event_count()
574 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_mem_access()
588 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_mem_access()
630 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_sw_incr()
676 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); in test_chained_counters()
679 report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #1"); in test_chained_counters()
688 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); in test_chained_counters()
691 report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #2"); in test_chained_counters()
696 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); in test_chained_counters()
719 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); in test_chained_sw_incr()
738 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); in test_chained_sw_incr()
785 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_mem_access_reliability()
788 num_events = cntr_val - pre_overflow2; in test_mem_access_reliability()
791 num_events = cntr_val + all_set - pre_overflow2; in test_mem_access_reliability()
821 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
834 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
847 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
854 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
871 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
879 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
898 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
907 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
912 "32b->64b: CHAIN counter incremented and overflow"); in test_chain_promotion()
924 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
931 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
982 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
985 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
992 set_pmcr(pmu.pmcr_ro); in test_overflow_interrupt()
1006 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1008 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1014 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro); in test_overflow_interrupt()
1020 * promote to 64-b: in test_overflow_interrupt()
1033 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1041 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1057 * Ensure that the cycle counter progresses between back-to-back reads.
1092 * greater than or equal to 4 are supported by the in-line assembly code. The
1101 int loop = (num - 2) / 2; in measure_instrs()
1103 assert(num >= 4 && ((num - 2) % 2 == 0)); in measure_instrs()
1112 * it. Strict CPI checking is used to test -icount mode.
1157 printf(" avg=%-4"PRId64" %s=%-3"PRId64"\n", avg, in check_cpi()
1168 if (pmu.version == ID_DFR0_PMU_V3) { in pmccntr64_test()
1178 /* Return FALSE if no PMU found, otherwise return TRUE */
1184 pmu.version = get_pmu_version(); in pmu_probe()
1185 if (pmu.version == ID_DFR0_PMU_NOTIMPL || pmu.version == ID_DFR0_PMU_IMPDEF) in pmu_probe()
1188 report_info("PMU version: 0x%x", pmu.version); in pmu_probe()
1192 report_info("PMU implementer/ID code: %#"PRIx32"(\"%c\")/%#"PRIx32, in pmu_probe()
1197 /* store read-only and RES0 fields of the PMCR bottom-half*/ in pmu_probe()
1198 pmu.pmcr_ro = pmcr & 0xFFFFFF00; in pmu_probe()
1199 pmu.nb_implemented_counters = in pmu_probe()
1202 pmu.nb_implemented_counters); in pmu_probe()
1222 const char *prefix = overflow_at_64bits ? "64-bit overflows" in run_event_test()
1223 : "32-bit overflows"; in run_event_test()
1233 printf("No PMU found, test skipped...\n"); in main()
1240 report_prefix_push("pmu"); in main()
1242 if (strcmp(argv[1], "cycle-counter") == 0) { in main()
1251 } else if (strcmp(argv[1], "pmu-event-introspection") == 0) { in main()
1255 } else if (strcmp(argv[1], "pmu-event-counter-config") == 0) { in main()
1259 } else if (strcmp(argv[1], "pmu-basic-event-count") == 0) { in main()
1262 } else if (strcmp(argv[1], "pmu-mem-access-reliability") == 0) { in main()
1265 } else if (strcmp(argv[1], "pmu-mem-access") == 0) { in main()
1268 } else if (strcmp(argv[1], "pmu-sw-incr") == 0) { in main()
1271 } else if (strcmp(argv[1], "pmu-chained-counters") == 0) { in main()
1273 } else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) { in main()
1275 } else if (strcmp(argv[1], "pmu-chain-promotion") == 0) { in main()
1277 } else if (strcmp(argv[1], "pmu-overflow-interrupt") == 0) { in main()
1281 report_abort("Unknown sub-test '%s'", argv[1]); in main()