Lines Matching +full:pmu +full:- +full:event +full:- +full:counter +full:- +full:config
2 * Test the ARM Performance Monitors Unit (PMU).
4 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
43 /* Some PMU events */
75 #define PRE_OVERFLOW2_32 (ALL_SET_32 - COUNT - MARGIN)
76 #define PRE_OVERFLOW2_64 (ALL_SET_64 - COUNT - MARGIN)
86 struct pmu { struct
98 static struct pmu pmu; argument
176 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); in pmu_reset()
186 /* event counter tests only implemented for aarch64 */
260 * The low 32-bits of PMCEID0/1 respectively describe in is_event_supported()
261 * event support for events 0-31/32-63. Their High in is_event_supported()
262 * 32-bits describe support for extended events in is_event_supported()
276 report_info("event 0x%x is not supported", n); in is_event_supported()
284 if (!pmu.nb_implemented_counters) { in test_event_introspection()
285 report_skip("No event counter, skip ..."); in test_event_introspection()
295 if (pmu.version >= ID_DFR0_PMU_V3_8_1) { in test_event_introspection()
373 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); in pmu_reset()
388 if (!pmu.nb_implemented_counters) { in test_event_counter_config()
389 report_skip("No event counter, skip ..."); in test_event_counter_config()
397 * select counter 0 in test_event_counter_config()
400 /* program this counter to count unsupported event */ in test_event_counter_config()
408 /* try to configure an unsupported event within the range [0x0, 0x3F] */ in test_event_counter_config()
418 /* select counter 0 */ in test_event_counter_config()
420 /* program this counter to count unsupported event */ in test_event_counter_config()
422 /* read the counter value */ in test_event_counter_config()
425 "read of a counter programmed with unsupported event"); in test_event_counter_config()
432 if (pmu.nb_implemented_counters < nb_events) { in satisfy_prerequisites()
434 pmu.nb_implemented_counters); in satisfy_prerequisites()
440 report_skip("Skip test as event 0x%x is not supported", in satisfy_prerequisites()
451 * Bits [63:0] are always incremented for 64-bit counters, in pmevcntr_mask()
452 * even if the PMU is configured to generate an overflow at in pmevcntr_mask()
456 * pseudo-code in the ARM ARM DDI 0487I.a, section J1.1.1. in pmevcntr_mask()
458 if (pmu.version >= ID_DFR0_PMU_V3_8_5) in pmevcntr_mask()
466 if (overflow_at_64bits && pmu.version < ID_DFR0_PMU_V3_8_5) { in check_overflow_prerequisites()
486 implemented_counter_mask = BIT(pmu.nb_implemented_counters) - 1; in test_basic_event_count()
499 * clear cycle and all event counters and allow counter enablement in test_basic_event_count()
502 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P | pmcr_lp); in test_basic_event_count()
504 report(get_pmcr() == (pmu.pmcr_ro | PMU_PMCR_LC | pmcr_lp), "pmcr: reset counters"); in test_basic_event_count()
506 /* Preset counter #0 to pre overflow value to trigger an overflow */ in test_basic_event_count()
509 "counter #0 preset to pre-overflow value"); in test_basic_event_count()
510 report(!read_regn_el0(pmevcntr, 1), "counter #1 is 0"); in test_basic_event_count()
538 /* enable overflow interrupts on all event counters */ in test_basic_event_count()
545 precise_instrs_loop(20, pmu.pmcr_ro | PMU_PMCR_E); in test_basic_event_count()
547 report_info("counter #0 is 0x%lx (CPU_CYCLES)", in test_basic_event_count()
549 report_info("counter #1 is 0x%lx (INST_RETIRED)", in test_basic_event_count()
574 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_mem_access()
575 report_info("counter #0 is 0x%lx (MEM_ACCESS)", read_regn_el0(pmevcntr, 0)); in test_mem_access()
576 report_info("counter #1 is 0x%lx (MEM_ACCESS)", read_regn_el0(pmevcntr, 1)); in test_mem_access()
588 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_mem_access()
622 report_info("SW_INCR counter #0 has value 0x%lx", read_regn_el0(pmevcntr, 0)); in test_sw_incr()
630 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_sw_incr()
637 report(read_regn_el0(pmevcntr, 0) == cntr0, "counter #0 after + 100 SW_INCR"); in test_sw_incr()
638 report(read_regn_el0(pmevcntr, 1) == 100, "counter #1 after + 100 SW_INCR"); in test_sw_incr()
639 report_info("counter values after 100 SW_INCR #0=0x%lx #1=0x%lx", in test_sw_incr()
642 "overflow on counter #0 after 100 SW_INCR"); in test_sw_incr()
647 write_sysreg_s(BIT(even + 1), PMCNTENSET_EL0); /* Enable the high counter first */ in enable_chain_counter()
649 write_sysreg_s(BIT(even), PMCNTENSET_EL0); /* Enable the low counter */ in enable_chain_counter()
655 write_sysreg_s(BIT(even), PMCNTENCLR_EL0); /* Disable the low counter first*/ in disable_chain_counter()
657 write_sysreg_s(BIT(even + 1), PMCNTENCLR_EL0); /* Disable the high counter */ in disable_chain_counter()
676 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); in test_chained_counters()
678 report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented"); in test_chained_counters()
688 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); in test_chained_counters()
690 report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2"); in test_chained_counters()
696 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); in test_chained_counters()
698 report(read_regn_el0(pmevcntr, 1) == 0, "CHAIN counter #1 wrapped"); in test_chained_counters()
719 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); in test_chained_sw_incr()
728 "overflow and chain counter incremented after 100 SW_INCR/CHAIN"); in test_chained_sw_incr()
732 /* 64b SW_INCR and overflow on CHAIN counter*/ in test_chained_sw_incr()
738 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); in test_chained_sw_incr()
785 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_mem_access_reliability()
788 num_events = cntr_val - pre_overflow2; in test_mem_access_reliability()
790 /* unexpected counter overflow */ in test_mem_access_reliability()
791 num_events = cntr_val + all_set - pre_overflow2; in test_mem_access_reliability()
813 /* Only enable CHAIN counter */ in test_chain_promotion()
821 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
824 "chain counter not counting if even counter is disabled"); in test_chain_promotion()
827 /* Only enable even counter */ in test_chain_promotion()
834 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
837 "odd counter did not increment on overflow if disabled"); in test_chain_promotion()
847 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
850 /* disable the CHAIN event */ in test_chain_promotion()
852 write_sysreg_s(0x1, PMCNTENSET_EL0); /* Enable the low counter */ in test_chain_promotion()
854 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
859 "CHAIN counter #1 shouldn't have incremented"); in test_chain_promotion()
871 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
874 /* Disable the low counter first and enable the chain counter */ in test_chain_promotion()
879 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
885 "CHAIN counter enabled: CHAIN counter was incremented and overflow"); in test_chain_promotion()
898 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
907 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
912 "32b->64b: CHAIN counter incremented and overflow"); in test_chain_promotion()
924 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
931 mem_access_loop(addr, COUNT, pmu.pmcr_ro | PMU_PMCR_E); in test_chain_promotion()
934 "overflow is expected on counter 0"); in test_chain_promotion()
982 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
985 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
992 set_pmcr(pmu.pmcr_ro); in test_overflow_interrupt()
1006 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1008 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1014 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro); in test_overflow_interrupt()
1020 * promote to 64-b: in test_overflow_interrupt()
1033 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1036 /* overflow on odd counter */ in test_overflow_interrupt()
1041 mem_access_loop(addr, COUNT_INT, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); in test_overflow_interrupt()
1044 "expect overflow interrupt on even counter"); in test_overflow_interrupt()
1046 "Odd counter did not change"); in test_overflow_interrupt()
1049 "expect overflow interrupt on even and odd counter"); in test_overflow_interrupt()
1051 "Odd counter wrapped"); in test_overflow_interrupt()
1057 * Ensure that the cycle counter progresses between back-to-back reads.
1063 /* init before event access, this test only cares about cycle count */ in check_cycles_increase()
1092 * greater than or equal to 4 are supported by the in-line assembly code. The
1094 * for example for the cycle counter or event counters to be reset). At the end
1096 * counting, allowing the cycle counter or event counters to be read at the
1101 int loop = (num - 2) / 2; in measure_instrs()
1103 assert(num >= 4 && ((num - 2) % 2 == 0)); in measure_instrs()
1109 * cycle counter progresses (similar to check_cycles_increase() but with more
1112 * it. Strict CPI checking is used to test -icount mode.
1118 /* init before event access, this test only cares about cycle count */ in check_cpi()
1148 * 32 bits of the cycle counter to make sure in check_cpi()
1157 printf(" avg=%-4"PRId64" %s=%-3"PRId64"\n", avg, in check_cpi()
1168 if (pmu.version == ID_DFR0_PMU_V3) { in pmccntr64_test()
1178 /* Return FALSE if no PMU found, otherwise return TRUE */
1184 pmu.version = get_pmu_version(); in pmu_probe()
1185 if (pmu.version == ID_DFR0_PMU_NOTIMPL || pmu.version == ID_DFR0_PMU_IMPDEF) in pmu_probe()
1188 report_info("PMU version: 0x%x", pmu.version); in pmu_probe()
1192 report_info("PMU implementer/ID code: %#"PRIx32"(\"%c\")/%#"PRIx32, in pmu_probe()
1197 /* store read-only and RES0 fields of the PMCR bottom-half*/ in pmu_probe()
1198 pmu.pmcr_ro = pmcr & 0xFFFFFF00; in pmu_probe()
1199 pmu.nb_implemented_counters = in pmu_probe()
1201 report_info("Implements %d event counters", in pmu_probe()
1202 pmu.nb_implemented_counters); in pmu_probe()
1222 const char *prefix = overflow_at_64bits ? "64-bit overflows" in run_event_test()
1223 : "32-bit overflows"; in run_event_test()
1233 printf("No PMU found, test skipped...\n"); in main()
1240 report_prefix_push("pmu"); in main()
1242 if (strcmp(argv[1], "cycle-counter") == 0) { in main()
1251 } else if (strcmp(argv[1], "pmu-event-introspection") == 0) { in main()
1255 } else if (strcmp(argv[1], "pmu-event-counter-config") == 0) { in main()
1259 } else if (strcmp(argv[1], "pmu-basic-event-count") == 0) { in main()
1262 } else if (strcmp(argv[1], "pmu-mem-access-reliability") == 0) { in main()
1265 } else if (strcmp(argv[1], "pmu-mem-access") == 0) { in main()
1268 } else if (strcmp(argv[1], "pmu-sw-incr") == 0) { in main()
1271 } else if (strcmp(argv[1], "pmu-chained-counters") == 0) { in main()
1273 } else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) { in main()
1275 } else if (strcmp(argv[1], "pmu-chain-promotion") == 0) { in main()
1277 } else if (strcmp(argv[1], "pmu-overflow-interrupt") == 0) { in main()
1281 report_abort("Unknown sub-test '%s'", argv[1]); in main()