4  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
72  * produce 32b overflow and 2nd @COUNT iterations do. To accommodate
75 #define PRE_OVERFLOW2_32		(ALL_SET_32 - COUNT - MARGIN)
76 #define PRE_OVERFLOW2_64		(ALL_SET_64 - COUNT - MARGIN)
153  * Extra instructions inserted by the compiler would be difficult to compensate
155  * to start and stop counting. isb instructions were inserted to make sure
156  * pmccntr read after this function returns the exact instructions executed in
224  * Extra instructions inserted by the compiler would be difficult to compensate
226  * to start and stop counting. isb instructions are inserted to make sure
227  * pmccntr read after this function returns the exact instructions executed
260 	 * The low 32-bits of PMCEID0/1 respectively describe  in is_event_supported()
261 	 * event support for events 0-31/32-63. Their High  in is_event_supported()
262 	 * 32-bits describe support for extended events  in is_event_supported()
305  * Extra instructions inserted by the compiler would be difficult to compensate
307  * to start and stop counting. isb instructions are inserted to make sure
308  * pmccntr read after this function returns the exact instructions executed
396 	 * Test setting through PMESELR/PMXEVTYPER and PMEVTYPERn read,  in test_event_counter_config()
400 	/* program this counter to count unsupported event */  in test_event_counter_config()
408 	/* try to configure an unsupported event within the range [0x0, 0x3F] */  in test_event_counter_config()
420 	/* program this counter to count unsupported event */  in test_event_counter_config()
422 	/* read the counter value */  in test_event_counter_config()
425 		"read of a counter programmed with unsupported event");  in test_event_counter_config()
451 	 * Bits [63:0] are always incremented for 64-bit counters,  in pmevcntr_mask()
452 	 * even if the PMU is configured to generate an overflow at  in pmevcntr_mask()
456 	 * pseudo-code in the ARM ARM DDI 0487I.a, section J1.1.1.  in pmevcntr_mask()
486 	implemented_counter_mask = BIT(pmu.nb_implemented_counters) - 1;  in test_basic_event_count()
506 	/* Preset counter #0 to pre overflow value to trigger an overflow */  in test_basic_event_count()
509 		"counter #0 preset to pre-overflow value");  in test_basic_event_count()
513 	 * Enable all implemented counters and also attempt to enable  in test_basic_event_count()
690 	report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2");  in test_chained_counters()
761  * records the min/max access count to see how much the counting
788 			num_events = cntr_val - pre_overflow2;  in test_mem_access_reliability()
791 			num_events = cntr_val + all_set - pre_overflow2;  in test_mem_access_reliability()
888 	/* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */  in test_chain_promotion()
912 		"32b->64b: CHAIN counter incremented and overflow");  in test_chain_promotion()
915 	/* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */  in test_chain_promotion()
1020 	 * promote to 64-b:  in test_overflow_interrupt()
1022 	 * This only applies to the !overflow_at_64bits case, as  in test_overflow_interrupt()
1057  * Ensure that the cycle counter progresses between back-to-back reads.
1078 			printf("Read %"PRId64" then %"PRId64".\n", a, b);  in check_cycles_increase()
1092  * greater than or equal to 4 are supported by the in-line assembly code. The
1094  * for example for the cycle counter or event counters to be reset). At the end
1095  * of the exact instruction loop, zero is written to PMCR_EL0 to disable
1096  * counting, allowing the cycle counter or event counters to be read at the
1101 	int loop = (num - 2) / 2;  in measure_instrs()
1103 	assert(num >= 4 && ((num - 2) % 2 == 0));  in measure_instrs()
1109  * cycle counter progresses (similar to check_cycles_increase() but with more
1112  * it. Strict CPI checking is used to test -icount mode.
1148 				 * 32 bits of the cycle counter to make sure  in check_cpi()
1157 		printf(" avg=%-4"PRId64" %s=%-3"PRId64"\n", avg,  in check_cpi()
1173 			report_skip("Skipping unsafe pmccntr64 test. Set ERRATA_9e3f7a296940=y to enable.");  in pmccntr64_test()
1197 	/* store read-only and RES0 fields of the PMCR bottom-half*/  in pmu_probe()
1222 	const char *prefix = overflow_at_64bits ? "64-bit overflows"  in run_event_test()
1223 						: "32-bit overflows";  in run_event_test()
1242 	if (strcmp(argv[1], "cycle-counter") == 0) {  in main()
1251 	} else if (strcmp(argv[1], "pmu-event-introspection") == 0) {  in main()
1255 	} else if (strcmp(argv[1], "pmu-event-counter-config") == 0) {  in main()
1259 	} else if (strcmp(argv[1], "pmu-basic-event-count") == 0) {  in main()
1262 	} else if (strcmp(argv[1], "pmu-mem-access-reliability") == 0) {  in main()
1265 	} else if (strcmp(argv[1], "pmu-mem-access") == 0) {  in main()
1268 	} else if (strcmp(argv[1], "pmu-sw-incr") == 0) {  in main()
1271 	} else if (strcmp(argv[1], "pmu-chained-counters") == 0) {  in main()
1273 	} else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) {  in main()
1275 	} else if (strcmp(argv[1], "pmu-chain-promotion") == 0) {  in main()
1277 	} else if (strcmp(argv[1], "pmu-overflow-interrupt") == 0) {  in main()
1281 		report_abort("Unknown sub-test '%s'", argv[1]);  in main()