24 #define PMU_PMCR_E         (1 << 0)
25 #define PMU_PMCR_P         (1 << 1)
26 #define PMU_PMCR_C         (1 << 2)
27 #define PMU_PMCR_D         (1 << 3)
28 #define PMU_PMCR_X         (1 << 4)
29 #define PMU_PMCR_DP        (1 << 5)
30 #define PMU_PMCR_LC        (1 << 6)
31 #define PMU_PMCR_LP        (1 << 7)
71  * PRE_OVERFLOW2 is set so that 1st @COUNT iterations do not
116 #define PMXEVTYPER   __ACCESS_CP15(c9, 0, c13, 1)
117 #define PMCNTENSET   __ACCESS_CP15(c9, 0, c12, 1)
164 	"1:	subs	%[loop], %[loop], #1\n"  in precise_instrs_loop()
165 	"	bgt	1b\n"  in precise_instrs_loop()
236 	"1:	subs	%w[loop], %w[loop], #1\n"  in precise_instrs_loop()
237 	"	b.gt	1b\n"  in precise_instrs_loop()
246 #define PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
260 	 * The low 32-bits of PMCEID0/1 respectively describe  in is_event_supported()
273 	supported =  reg & (1UL << (n & 0x3F));  in is_event_supported()
320 	"1:     sub     x10, x10, #1\n"  in mem_access_loop()
323 	"       b.gt    1b\n"  in mem_access_loop()
348 				pmu_stats.bitmap |= 1 << i;  in irq_handler()
486 	implemented_counter_mask = BIT(pmu.nb_implemented_counters) - 1;  in test_basic_event_count()
491 	write_regn_el0(pmevtyper, 1, INST_RETIRED | PMEVTYPER_EXCLUDE_EL0);  in test_basic_event_count()
510 	report(!read_regn_el0(pmevcntr, 1), "counter #1 is 0");  in test_basic_event_count()
523 	/* Disable all counters but counters #0 and #1 */  in test_basic_event_count()
527 		"pmcntenset: just enabled #0 and #1");  in test_basic_event_count()
549 	report_info("counter #1 is 0x%lx (INST_RETIRED)",  in test_basic_event_count()
550 		    read_regn_el0(pmevcntr, 1));  in test_basic_event_count()
571 	write_regn_el0(pmevtyper, 1, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0);  in test_mem_access()
576 	report_info("counter #1 is 0x%lx (MEM_ACCESS)", read_regn_el0(pmevcntr, 1));  in test_mem_access()
578 	report((read_regn_el0(pmevcntr, 0) == read_regn_el0(pmevcntr, 1)) &&  in test_mem_access()
585 	write_regn_el0(pmevcntr, 1, pre_overflow);  in test_mem_access()
591 	report_info("cnt#0=0x%lx cnt#1=0x%lx overflow=0x%lx",  in test_mem_access()
592 			read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1),  in test_mem_access()
611 	write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0);  in test_sw_incr()
612 	/* enable counters #0 and #1 */  in test_sw_incr()
638 	report(read_regn_el0(pmevcntr, 1) == 100, "counter #1 after + 100 SW_INCR");  in test_sw_incr()
639 	report_info("counter values after 100 SW_INCR #0=0x%lx #1=0x%lx",  in test_sw_incr()
640 		    read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));  in test_sw_incr()
647 	write_sysreg_s(BIT(even + 1), PMCNTENSET_EL0); /* Enable the high counter first */  in enable_chain_counter()
657 	write_sysreg_s(BIT(even + 1), PMCNTENCLR_EL0); /* Disable the high counter */  in disable_chain_counter()
672 	write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);  in test_chained_counters()
678 	report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented");  in test_chained_counters()
679 	report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #1");  in test_chained_counters()
686 	write_regn_el0(pmevcntr, 1, 0x1);  in test_chained_counters()
690 	report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2");  in test_chained_counters()
694 	write_regn_el0(pmevcntr, 1, all_set);  in test_chained_counters()
698 	report(read_regn_el0(pmevcntr, 1) == 0, "CHAIN counter #1 wrapped");  in test_chained_counters()
706 	uint64_t cntr1 = (ALL_SET_32 + 1) & pmevcntr_mask();  in test_chained_sw_incr()
715 	write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);  in test_chained_sw_incr()
727 		(read_regn_el0(pmevcntr, 1) == 1),  in test_chained_sw_incr()
729 	report_info("overflow=0x%lx, #0=0x%lx #1=0x%lx", read_sysreg(pmovsclr_el0),  in test_chained_sw_incr()
730 		    read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));  in test_chained_sw_incr()
736 	write_regn_el0(pmevcntr, 1, ALL_SET_32);  in test_chained_sw_incr()
747 	       (read_regn_el0(pmevcntr, 1) == cntr1),  in test_chained_sw_incr()
749 	report_info("overflow=0x%lx, #0=0x%lx #1=0x%lx", read_sysreg(pmovsclr_el0),  in test_chained_sw_incr()
750 		    read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));  in test_chained_sw_incr()
753 	report_info("%s #1=0x%lx #0=0x%lx overflow=0x%lx", __s, \
754 		    read_regn_el0(pmevcntr, 1), \
817 	write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);  in test_chain_promotion()
836 	report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1),  in test_chain_promotion()
840 	/* 1st COUNT with CHAIN enabled, next COUNT with CHAIN disabled */  in test_chain_promotion()
848 	PRINT_REGS("After 1st loop");  in test_chain_promotion()
858 	report(!read_regn_el0(pmevcntr, 1),  in test_chain_promotion()
859 		"CHAIN counter #1 shouldn't have incremented");  in test_chain_promotion()
862 	/* 1st COUNT with CHAIN disabled, next COUNT with CHAIN enabled */  in test_chain_promotion()
872 	PRINT_REGS("After 1st loop");  in test_chain_promotion()
883 	report((read_regn_el0(pmevcntr, 1) == 1) &&  in test_chain_promotion()
892 	write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0);  in test_chain_promotion()
899 	PRINT_REGS("After 1st loop");  in test_chain_promotion()
903 	write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);  in test_chain_promotion()
904 	write_regn_el0(pmevcntr, 1, 0x0);  in test_chain_promotion()
910 	report((read_regn_el0(pmevcntr, 1) == 1) &&  in test_chain_promotion()
919 	write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);  in test_chain_promotion()
925 	PRINT_REGS("After 1st loop");  in test_chain_promotion()
928 	write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0);  in test_chain_promotion()
933 	report(read_sysreg(pmovsclr_el0) == 1,  in test_chain_promotion()
947 			if (pmu_stats.interrupts[i] != 1)  in expect_interrupts()
974 	write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0);  in test_overflow_interrupt()
977 	write_regn_el0(pmevcntr, 1, pre_overflow);  in test_overflow_interrupt()
1001 	write_regn_el0(pmevcntr, 1, pre_overflow);  in test_overflow_interrupt()
1017 		"overflow interrupts expected on #0 and #1");  in test_overflow_interrupt()
1025 	 * not incremented when PMCR.LP == 1.  in test_overflow_interrupt()
1030 	write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);  in test_overflow_interrupt()
1039 	write_regn_el0(pmevcntr, 1, all_set);  in test_overflow_interrupt()
1045 		report(read_regn_el0(pmevcntr, 1) == all_set,  in test_overflow_interrupt()
1050 		report(read_regn_el0(pmevcntr, 1) != all_set,  in test_overflow_interrupt()
1065 	set_pmcntenset(1 << PMU_CYCLE_IDX);  in check_cycles_increase()
1120 	set_pmcntenset(1 << PMU_CYCLE_IDX);  in check_cpi()
1242 	if (strcmp(argv[1], "cycle-counter") == 0) {  in main()
1243 		report_prefix_push(argv[1]);  in main()
1251 	} else if (strcmp(argv[1], "pmu-event-introspection") == 0) {  in main()
1252 		report_prefix_push(argv[1]);  in main()
1255 	} else if (strcmp(argv[1], "pmu-event-counter-config") == 0) {  in main()
1256 		report_prefix_push(argv[1]);  in main()
1259 	} else if (strcmp(argv[1], "pmu-basic-event-count") == 0) {  in main()
1260 		run_event_test(argv[1], test_basic_event_count, false);  in main()
1261 		run_event_test(argv[1], test_basic_event_count, true);  in main()
1262 	} else if (strcmp(argv[1], "pmu-mem-access-reliability") == 0) {  in main()
1263 		run_event_test(argv[1], test_mem_access_reliability, false);  in main()
1264 		run_event_test(argv[1], test_mem_access_reliability, true);  in main()
1265 	} else if (strcmp(argv[1], "pmu-mem-access") == 0) {  in main()
1266 		run_event_test(argv[1], test_mem_access, false);  in main()
1267 		run_event_test(argv[1], test_mem_access, true);  in main()
1268 	} else if (strcmp(argv[1], "pmu-sw-incr") == 0) {  in main()
1269 		run_event_test(argv[1], test_sw_incr, false);  in main()
1270 		run_event_test(argv[1], test_sw_incr, true);  in main()
1271 	} else if (strcmp(argv[1], "pmu-chained-counters") == 0) {  in main()
1272 		run_event_test(argv[1], test_chained_counters, false);  in main()
1273 	} else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) {  in main()
1274 		run_event_test(argv[1], test_chained_sw_incr, false);  in main()
1275 	} else if (strcmp(argv[1], "pmu-chain-promotion") == 0) {  in main()
1276 		run_event_test(argv[1], test_chain_promotion, false);  in main()
1277 	} else if (strcmp(argv[1], "pmu-overflow-interrupt") == 0) {  in main()
1278 		run_event_test(argv[1], test_overflow_interrupt, false);  in main()
1279 		run_event_test(argv[1], test_overflow_interrupt, true);  in main()
1281 		report_abort("Unknown sub-test '%s'", argv[1]);  in main()