4  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
75 #define PRE_OVERFLOW2_32		(ALL_SET_32 - COUNT - MARGIN)
76 #define PRE_OVERFLOW2_64		(ALL_SET_64 - COUNT - MARGIN)
126 static inline void set_pmcr(uint32_t v) { write_sysreg(v, PMCR); }  in set_pmcr()  argument
127 static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, PMCNTENSET); }  in set_pmcntenset()  argument
211 static inline void set_pmcr(uint32_t v) { write_sysreg(v, pmcr_el0); }  in set_pmcr()  argument
213 static inline void set_pmccntr(uint64_t v) { write_sysreg(v, pmccntr_el0); }  in set_pmccntr()  argument
214 static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, pmcntenset_el0); }  in set_pmcntenset()  argument
215 static inline void set_pmccfiltr(uint32_t v) { write_sysreg(v, pmccfiltr_el0); }  in set_pmccfiltr()  argument
260 	 * The low 32-bits of PMCEID0/1 respectively describe  in is_event_supported()
261 	 * event support for events 0-31/32-63. Their High  in is_event_supported()
262 	 * 32-bits describe support for extended events  in is_event_supported()
451 	 * Bits [63:0] are always incremented for 64-bit counters,  in pmevcntr_mask()
456 	 * pseudo-code in the ARM ARM DDI 0487I.a, section J1.1.1.  in pmevcntr_mask()
486 	implemented_counter_mask = BIT(pmu.nb_implemented_counters) - 1;  in test_basic_event_count()
509 		"counter #0 preset to pre-overflow value");  in test_basic_event_count()
788 			num_events = cntr_val - pre_overflow2;  in test_mem_access_reliability()
791 			num_events = cntr_val + all_set - pre_overflow2;  in test_mem_access_reliability()
912 		"32b->64b: CHAIN counter incremented and overflow");  in test_chain_promotion()
1020 	 * promote to 64-b:  in test_overflow_interrupt()
1057  * Ensure that the cycle counter progresses between back-to-back reads.
1092  * greater than or equal to 4 are supported by the in-line assembly code. The
1101 	int loop = (num - 2) / 2;  in measure_instrs()
1103 	assert(num >= 4 && ((num - 2) % 2 == 0));  in measure_instrs()
1112  * it. Strict CPI checking is used to test -icount mode.
1157 		printf(" avg=%-4"PRId64" %s=%-3"PRId64"\n", avg,  in check_cpi()
1197 	/* store read-only and RES0 fields of the PMCR bottom-half*/  in pmu_probe()
1222 	const char *prefix = overflow_at_64bits ? "64-bit overflows"  in run_event_test()
1223 						: "32-bit overflows";  in run_event_test()
1242 	if (strcmp(argv[1], "cycle-counter") == 0) {  in main()
1251 	} else if (strcmp(argv[1], "pmu-event-introspection") == 0) {  in main()
1255 	} else if (strcmp(argv[1], "pmu-event-counter-config") == 0) {  in main()
1259 	} else if (strcmp(argv[1], "pmu-basic-event-count") == 0) {  in main()
1262 	} else if (strcmp(argv[1], "pmu-mem-access-reliability") == 0) {  in main()
1265 	} else if (strcmp(argv[1], "pmu-mem-access") == 0) {  in main()
1268 	} else if (strcmp(argv[1], "pmu-sw-incr") == 0) {  in main()
1271 	} else if (strcmp(argv[1], "pmu-chained-counters") == 0) {  in main()
1273 	} else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) {  in main()
1275 	} else if (strcmp(argv[1], "pmu-chain-promotion") == 0) {  in main()
1277 	} else if (strcmp(argv[1], "pmu-overflow-interrupt") == 0) {  in main()
1281 		report_abort("Unknown sub-test '%s'", argv[1]);  in main()