Lines Matching +full:0 +full:x0
33 * Bootloader params are in x0-x3. See kernel doc
102 bl setup // x0 is the addr of the dtb
105 adrp x0, __argc
106 ldr w0, [x0, :lo12:__argc]
134 * x0 -- return code
155 \instr #0
160 stp x0, x1, [x10, #0]
181 adrp x0, auxinfo
182 ldr x0, [x0, :lo12:auxinfo + 8]
183 and x0, x0, #AUXINFO_MMU_OFF
189 mov x0, #(3 << 20)
190 orr x0, x0, #(3 << 16)
191 msr cpacr_el1, x0
198 cbnz x0, 1f
199 adrp x0, mmu_idmap
200 ldr x0, [x0, :lo12:mmu_idmap]
205 adrp x0, secondary_data
206 ldr x0, [x0, :lo12:secondary_data]
207 mov sp, x0
212 /* x0 is now the entry function, run it */
213 blr x0
224 * x0 is the base address of the translation table
235 * n = AttrIndx[2:0]
272 ldr x1, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
273 MAIR(0x04, MT_DEVICE_nGnRE) | \
274 MAIR(0x0c, MT_DEVICE_GRE) | \
275 MAIR(0x44, MT_NORMAL_NC) | \
276 MAIR(0xff, MT_NORMAL) | \
277 MAIR(0xbb, MT_NORMAL_WT) | \
278 MAIR(0x08, MT_DEVICE_nGRE) | \
279 MAIR(0xf0, MT_NORMAL_TAGGED)
283 msr ttbr0_el1, x0
298 mrs x0, sctlr_el1
299 bic x0, x0, SCTLR_EL1_M
300 msr sctlr_el1, x0
304 adrp x0, __phys_offset
305 ldr x0, [x0, :lo12:__phys_offset]
308 sub x1, x1, x0
309 dcache_by_line_op civac, sy, x0, x1, x2, x3
334 stp x0, x1, [sp, #-S_FRAME_SIZE]!
370 mov x0, \vec
400 ldp x0, x1, [sp], #S_FRAME_SIZE
408 vector_stub el1t_sync, 0