kvm-unit-tests/arm/cstart.S

11 #include <asm/asm-offsets.h>
12 #include <asm/pgtable-hwdef.h>
16 #define THREAD_START_SP ((THREAD_SIZE - S_FRAME_SIZE * 8) & ~7)
61 	 * bootloader params are in r0-r2
68 	 * put the dtb in r0. This allows setup to be consistent
72 	push	{r0-r1}
81 	pop	{r0-r1}
101  *   r0 -- function_id
102  *   r1 -- arg0
103  *   r2 -- arg1
104  *   r3 -- arg2
105  *   [sp] - arg3
106  *   [sp + #4] - arg4
107  *   [sp + #8] - arg5
108  *   [sp + #12] - arg6
109  *   [sp + #16] - arg7
110  *   [sp + #20] - arg8
111  *   [sp + #24] - arg9
112  *   [sp + #28] - arg10
113  *   [sp + #32] - result (as a pointer to a struct smccc_result)
116  *   r0 -- return code
119  *   result.r0 -- return code
120  *   result.r1 -- r1
121  *   result.r2 -- r2
122  *   result.r3 -- r3
123  *   result.r4 -- r4
124  *   result.r5 -- r5
125  *   result.r6 -- r6
126  *   result.r7 -- r7
127  *   result.r8 -- r8
128  *   result.r9 -- r9
132 	push	{r4-r11}
133 	ldm	r12, {r4-r11}
138 	stm	r10, {r0-r9}
140 	pop	{r4-r11}
153 	/* Enable full access to CP10 and CP11: */
157 	/* Set the FPEXC.EN bit to enable Advanced SIMD and VFP: */
206  *     (r0 - lo, r1 - hi) is the base address of the translation table
281 	mcr	p15, 0, r2, c1, c0, 0	@ write SCTLR
283 	mcr	p15, 0, r2, c12, c0, 0	@ write VBAR
295 	msr	cpsr_cxsf, r2		@ back to svc mode
302  *   arch/arm/kernel/entry-armv.S
306  * to the base of that region in exceptions_init.
330 	/* Branch to handler in SVC mode */
362 	 * Branch to handler, still in SVC mode.
375 	/* store registers r0-r12 */
376 	stmia	sp, { r0-r12 }		@ stored wrong r0 and r1, fix later
398 	mov	r2, #-1
413 	 * make sure we restore sp_svc on mode change. No need to
421 	ldmia	sp, { r0-pc }^