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0632e555 |
| 27-Jul-2015 |
Aurelien Jarno <aurelien@aurel32.net> |
tcg: rename trunc_shr_i32 into trunc_shr_i64_i32
The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32, and the name in the README doesn't match the name offered to the frontends.
tcg: rename trunc_shr_i32 into trunc_shr_i64_i32
The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32, and the name in the README doesn't match the name offered to the frontends.
Always use the long name to make it clear it is a size changing op.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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006f8638 |
| 05-May-2015 |
Paolo Bonzini <pbonzini@redhat.com> |
tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS
This will be used to size the TLB when more than 8 MMU modes are used by the target. Limitations come from the limited size of the immediate fields (which
tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS
This will be used to size the TLB when more than 8 MMU modes are used by the target. Limitations come from the limited size of the immediate fields (which sometimes, as in the case of Aarch64, extend to instructions that shift the immediate).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1424436345-37924-2-git-send-email-pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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224f9fd4 |
| 30-Apr-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc: Merge cache-utils into the backend
As a "utility", it only supported ppc, and in a way that other tcg backends provided directly in tcg-target.h. Removing this disparity is easier now that
tcg-ppc: Merge cache-utils into the backend
As a "utility", it only supported ppc, and in a way that other tcg backends provided directly in tcg-target.h. Removing this disparity is easier now that the two ppc backends are merged.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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40d964b5 |
| 30-Apr-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc: Rename the tcg/ppc64 backend
The other tcg backends that support 32- and 64-bit modes use the 32-bit name for the port. Follow suit.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-b
tcg-ppc: Rename the tcg/ppc64 backend
The other tcg backends that support 32- and 64-bit modes use the 32-bit name for the port. Follow suit.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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8fa391a0 |
| 26-Mar-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Support mulsh_i32
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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abcf61c4 |
| 30-Apr-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Merge ppc32 brcond2, setcond2, muluh
Now passes tcg_add_target_add_op_defs assertions, but not complete enough to function.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richa
tcg-ppc64: Merge ppc32 brcond2, setcond2, muluh
Now passes tcg_add_target_add_op_defs assertions, but not complete enough to function.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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796f1a68 |
| 30-Apr-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Begin merging ppc32 with ppc64
Just enough to compile, assuming you edit config-host.mak manually. It will still abort at runtime, due to missing brcond2, setcond2, mulu2.
Tested-by: Tom
tcg-ppc64: Begin merging ppc32 with ppc64
Just enough to compile, assuming you edit config-host.mak manually. It will still abort at runtime, due to missing brcond2, setcond2, mulu2.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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a921fddc |
| 25-Mar-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Move call macros out of tcg-target.h
These values are private to tcg.c; we don't need to expose this nonsense to the translators.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by:
tcg-ppc64: Move call macros out of tcg-target.h
These values are private to tcg.c; we don't need to expose this nonsense to the translators.
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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3bf4a1ed |
| 25-Mar-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Make TCG_AREG0 and TCG_REG_CALL_STACK enum constants
Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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3d1b2ff6 |
| 29-May-2014 |
Richard Henderson <rth@twiddle.net> |
tcg: Remove TCG_TARGET_HAS_new_ldst
Since all backends have been converted, remove the compatibility code.
Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <r
tcg: Remove TCG_TARGET_HAS_new_ldst
Since all backends have been converted, remove the compatibility code.
Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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e083c4a2 |
| 28-Mar-2014 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Define TCG_TARGET_INSN_UNIT_SIZE
And use tcg pointer differencing functions as appropriate.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddl
tcg-ppc64: Define TCG_TARGET_INSN_UNIT_SIZE
And use tcg pointer differencing functions as appropriate.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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4bb7a41e |
| 10-Sep-2013 |
Richard Henderson <rth@twiddle.net> |
tcg: Add INDEX_op_trunc_shr_i32
Let the backend do something special for truncation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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02eb19d0 |
| 31-Mar-2014 |
Richard Henderson <rth@twiddle.net> |
tcg: Use HOST_WORDS_BIGENDIAN
Instead of rolling a local TCG_TARGET_WORDS_BIGENDIAN.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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1768ec06 |
| 10-Sep-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Support new ldst opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
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f713d6ad |
| 04-Sep-2013 |
Richard Henderson <rth@twiddle.net> |
tcg: Add qemu_ld_st_i32/64
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes.
Signed-off-by: Richard Henderson <rth@tw
tcg: Add qemu_ld_st_i32/64
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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32f5717f |
| 14-Aug-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Implement muluh, mulsh
Using these instead of mulu2 and muls2 lets us avoid having to argument overlap analysis in the backend. Normal register allocation will DTRT.
Reviewed-by: Aureli
tcg-ppc64: Implement muluh, mulsh
Using these instead of mulu2 and muls2 lets us avoid having to argument overlap analysis in the backend. Normal register allocation will DTRT.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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03271524 |
| 14-Aug-2013 |
Richard Henderson <rth@twiddle.net> |
tcg: Add muluh and mulsh opcodes
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ric
tcg: Add muluh and mulsh opcodes
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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5b9f72ab |
| 12-Mar-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Don't implement rem
Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
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ca675f46 |
| 12-Mar-2013 |
Richard Henderson <rth@twiddle.net> |
tcg: Split rem requirement from div requirement
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically.
Reviewed-b
tcg: Split rem requirement from div requirement
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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6645c147 |
| 05-Mar-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Implement mulu2/muls2_i64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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6c858762 |
| 04-Mar-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Implement add2/sub2_i64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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027ffea9 |
| 01-Feb-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Implement movcond
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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33de9ed2 |
| 31-Jan-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Implement deposit
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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ce1010d6 |
| 31-Jan-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Implement compound logicals
Mostly copied from the ppc32 port.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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68aebd45 |
| 31-Jan-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-ppc64: Implement bswap64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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