History log of /qemu/target/ppc/excp_helper.c (Results 151 – 175 of 324)
Revision Date Author Comments
# e670f6d8 20-Feb-2022 Peter Maydell <peter.maydell@linaro.org>

Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into staging

ppc-7.0 queue

* target/ppc: SPR registration cleanups (Fabiano)
* ppc: nested KVM HV for spapr virtual hypervisor

Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into staging

ppc-7.0 queue

* target/ppc: SPR registration cleanups (Fabiano)
* ppc: nested KVM HV for spapr virtual hypervisor (Nicholas)
* spapr: nvdimm: Introduce spapr-nvdimm device (Shivaprasad)

# gpg: Signature made Fri 18 Feb 2022 07:59:29 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-ppc-20220218: (39 commits)
target/ppc: Move common SPR functions out of cpu_init
target/ppc: cpu_init: Move check_pow and QOM macros to a header
target/ppc: cpu_init: Move SPR registration macros to a header
target/ppc: cpu_init: Expose some SPR registration helpers
target/ppc: Rename spr_tcg.h to spr_common.h
target/ppc: cpu_init: Remove register_usprg3_sprs
target/ppc: cpu_init: Rename register_ne_601_sprs
target/ppc: cpu_init: Reuse init_proc_745 for the 755
target/ppc: cpu_init: Reuse init_proc_604 for the 604e
target/ppc: cpu_init: Reuse init_proc_603 for the e300
target/ppc: cpu_init: Move 604e SPR registration into a function
target/ppc: cpu_init: Move e300 SPR registration into a function
target/ppc: cpu_init: Move 755 L2 cache SPRs into a function
target/ppc: cpu_init: Deduplicate 7xx SPR registration
target/ppc: cpu_init: Deduplicate 745/755 SPR registration
target/ppc: cpu_init: Deduplicate 604 SPR registration
target/ppc: cpu_init: Deduplicate 603 SPR registration
target/ppc: cpu_init: Deduplicate 440 SPR registration
target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
target/ppc: cpu_init: Decouple G2 SPR registration from 755
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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# 7cebc5db 18-Feb-2022 Nicholas Piggin <npiggin@gmail.com>

target/ppc: Introduce a vhyp framework for nested HV support

Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using

target/ppc: Introduce a vhyp framework for nested HV support

Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).

HV exceptions can now be raised in the TCG spapr machine when running a
nested KVM HV guest. The main ones are the lev==1 syscall, the hdecr,
hdsi and hisi, hv fu, and hv emu, and h_virt external interrupts.

HV exceptions are intercepted in the exception handler code and instead
of causing interrupts in the guest and switching the machine to HV mode,
they go to the vhyp where it may exit the H_ENTER_NESTED hcall with the
interrupt vector numer as return value as required by the hcall API.

Address translation is provided by the 2-level page table walker that is
implemented for the bare metal radix MMU. The partition scope page table
is pointed to the L1's partition scope by the get_pate vhc method.

Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220216102545.1808018-9-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 3680e994 18-Feb-2022 Nicholas Piggin <npiggin@gmail.com>

target/ppc: Add powerpc_reset_excp_state helper

This moves the logic to reset the QEMU exception state into its own
function.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Pi

target/ppc: Add powerpc_reset_excp_state helper

This moves the logic to reset the QEMU exception state into its own
function.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-8-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 4c6cf6b2 18-Feb-2022 Nicholas Piggin <npiggin@gmail.com>

target/ppc: add helper for books vhyp hypercall handler

The virtual hypervisor currently always intercepts and handles
hypercalls but with a future change this will not always be the case.

Add a he

target/ppc: add helper for books vhyp hypercall handler

The virtual hypervisor currently always intercepts and handles
hypercalls but with a future change this will not always be the case.

Add a helper for the test so the logic is abstracted from the mechanism.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220216102545.1808018-7-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# cc5ce8b8 13-Feb-2022 Peter Maydell <peter.maydell@linaro.org>

Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220210' into staging

ppc-7.0 queue

* Exception model rework (Fabiano)
* Unused CPU models removal (Fabiano and Cédric)
* Fix for VOF i

Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220210' into staging

ppc-7.0 queue

* Exception model rework (Fabiano)
* Unused CPU models removal (Fabiano and Cédric)
* Fix for VOF installation (Alexey)
* Misc fixes

# gpg: Signature made Thu 10 Feb 2022 12:59:07 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-ppc-20220210: (42 commits)
spapr/vof: Install rom and nvram binaries
docs: rstfy confidential guest documentation
target/ppc: Change VSX instructions behavior to fill with zeros
target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail
target/ppc: Assert if MSR bits differ from msr_mask during exceptions
target/ppc: powerpc_excp: Move common code to the caller function
target/ppc: Remove powerpc_excp_legacy
target/ppc: 7xx: Set SRRs directly in exception code
target/ppc: 7xx: Software TLB cleanup
target/ppc: 7xx: System Reset cleanup
target/ppc: 7xx: System Call exception cleanup
target/ppc: 7xx: Program exception cleanup
target/ppc: 7xx: External interrupt cleanup
target/ppc: 7xx: Machine Check exception cleanup
target/ppc: Simplify powerpc_excp_7xx
target/ppc: Introduce powerpc_excp_7xx
target/ppc: Merge 7x5 and 7x0 exception model IDs
target/ppc: 6xx: Set SRRs directly in exception code
target/ppc: 6xx: Software TLB exceptions cleanup
target/ppc: 6xx: System Reset interrupt cleanup
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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# 10895ab6 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail

We don't really need to check for exception model while applying
AIL. We can check the lpcr_mask for the presence of
LPCR_AIL/LP

target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail

We don't really need to check for exception model while applying
AIL. We can check the lpcr_mask for the presence of
LPCR_AIL/LPCR_HAIL.

This removes one more instance of passing the exception model ID
around.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220207183036.1507882-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# fce9fbaf 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: Assert if MSR bits differ from msr_mask during exceptions

We currently abort QEMU during the dispatch of an interrupt if we try
to set MSR_HV without having MSR_HVB in the msr_mask. I th

target/ppc: Assert if MSR bits differ from msr_mask during exceptions

We currently abort QEMU during the dispatch of an interrupt if we try
to set MSR_HV without having MSR_HVB in the msr_mask. I think we
should verify this for all MSR bits. There is no reason to ever have a
MSR bit set if the corresponding bit is not set in that CPU's
msr_mask.

Note that this is not about the emulated code setting reserved
bits. We clear the new_msr when starting to dispatch an exception, so
if we end up with bits not present in the msr_mask that is a QEMU
programming error.

I kept the HSRR verification for BookS because it is the only CPU
family that has HSRRs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220207183036.1507882-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# c6eaac89 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: powerpc_excp: Move common code to the caller function

Make the cpu-specific powerpc_excp_* functions a bit simpler by moving
the bounds check and logging to powerpc_excp.

Signed-off-by:

target/ppc: powerpc_excp: Move common code to the caller function

Make the cpu-specific powerpc_excp_* functions a bit simpler by moving
the bounds check and logging to powerpc_excp.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220207183036.1507882-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 28091374 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: Remove powerpc_excp_legacy

Now that all CPU families have their own separate exception
dispatching code we can remove powerpc_excp_legacy.

Signed-off-by: Fabiano Rosas <farosas@linux.ib

target/ppc: Remove powerpc_excp_legacy

Now that all CPU families have their own separate exception
dispatching code we can remove powerpc_excp_legacy.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220207183036.1507882-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# fe4b5c4c 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 7xx: Set SRRs directly in exception code

The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <far

target/ppc: 7xx: Set SRRs directly in exception code

The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 7df40c54 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 7xx: Software TLB cleanup

This code applies only to the 7xx CPUs, so we can remove the switch
statement.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430

target/ppc: 7xx: Software TLB cleanup

This code applies only to the 7xx CPUs, so we can remove the switch
statement.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 3c3fa438 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 7xx: System Reset cleanup

Thre is no HV support in the 7xx.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com>
Signed-off-

target/ppc: 7xx: System Reset cleanup

Thre is no HV support in the 7xx.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 3b578635 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 7xx: System Call exception cleanup

Remove the BookE code and add a comment explaining why we need to keep
hypercall support even though this CPU does not have a hypervisor
mode.

Signed-

target/ppc: 7xx: System Call exception cleanup

Remove the BookE code and add a comment explaining why we need to keep
hypercall support even though this CPU does not have a hypervisor
mode.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# ab369390 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 7xx: Program exception cleanup

There's no ESR in the 7xx.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-7-farosas@linux.ibm.com>
Signed-off-by

target/ppc: 7xx: Program exception cleanup

There's no ESR in the 7xx.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# a53ce465 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 7xx: External interrupt cleanup

There is no MSR_HV in the 7xx so remove the LPES0 handling.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-6-fa

target/ppc: 7xx: External interrupt cleanup

There is no MSR_HV in the 7xx so remove the LPES0 handling.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 784f5a34 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 7xx: Machine Check exception cleanup

There's no MSR_HV in the 7xx.

Also remove 40x and BookE code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457

target/ppc: 7xx: Machine Check exception cleanup

There's no MSR_HV in the 7xx.

Also remove 40x and BookE code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 93848d6a 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: Simplify powerpc_excp_7xx

Differences from the generic powerpc_excp code:

- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hy

target/ppc: Simplify powerpc_excp_7xx

Differences from the generic powerpc_excp code:

- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.

Exceptions used:

POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DLTLB
POWERPC_EXCP_DSI
POWERPC_EXCP_DSTLB
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_IFTLB
POWERPC_EXCP_ISI
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# ccfca2fc 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: Introduce powerpc_excp_7xx

Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs
(740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies
powerpc_excp_legacy ve

target/ppc: Introduce powerpc_excp_7xx

Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs
(740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies
powerpc_excp_legacy verbatim so the next one has a clean diff.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# fd7dc4bb 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: Merge 7x5 and 7x0 exception model IDs

Since we've split the exception code by exception model, the exception
model IDs are becoming less useful. These two can be merged.

Signed-off-by:

target/ppc: Merge 7x5 and 7x0 exception model IDs

Since we've split the exception code by exception model, the exception
model IDs are becoming less useful. These two can be merged.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# c50eaed1 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 6xx: Set SRRs directly in exception code

The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <far

target/ppc: 6xx: Set SRRs directly in exception code

The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 8f8c7932 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 6xx: Software TLB exceptions cleanup

This code applies only to the 6xx CPUs, so we can remove the switch
statement.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <202

target/ppc: 6xx: Software TLB exceptions cleanup

This code applies only to the 6xx CPUs, so we can remove the switch
statement.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 000ac49a 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 6xx: System Reset interrupt cleanup

There is no HV support in the 6xx.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-10-farosas@linux.ibm.com>

target/ppc: 6xx: System Reset interrupt cleanup

There is no HV support in the 6xx.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# c0e1928d 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 6xx: System Call exception cleanup

There is no Hypervisor mode in the 6xx CPUs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-9-farosas@linux.

target/ppc: 6xx: System Call exception cleanup

There is no Hypervisor mode in the 6xx CPUs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 25fe5f75 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 6xx: Program exception cleanup

There's no ESR in the 6xx CPUs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-8-farosas@linux.ibm.com>
Signed-o

target/ppc: 6xx: Program exception cleanup

There's no ESR in the 6xx CPUs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 3189fa39 09-Feb-2022 Fabiano Rosas <farosas@linux.ibm.com>

target/ppc: 6xx: External interrupt cleanup

There's no Hypervisor mode in the 6xx, so remove all LPES0 logic.

Also remove BookE IRQ code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Messa

target/ppc: 6xx: External interrupt cleanup

There's no Hypervisor mode in the 6xx, so remove all LPES0 logic.

Also remove BookE IRQ code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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