| #
1eed09cb |
| 14-Jun-2009 |
Avi Kivity <avi@redhat.com> |
Remove io_index argument from cpu_register_io_memory()
The parameter is always zero except when registering the three internal
io regions (ROM, unassigned, notdirty). Remove the parameter to reduce
Remove io_index argument from cpu_register_io_memory()
The parameter is always zero except when registering the three internal
io regions (ROM, unassigned, notdirty). Remove the parameter to reduce
the API's power, thus facilitating future change.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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|
| #
2ac71179 |
| 08-May-2009 |
Paul Brook <paul@codesourcery.com> |
Replace cpu_abort with hw_error
Signed-off-by: Paul Brook <paul@codesourcery.com>
|
| #
e7786f27 |
| 07-Feb-2009 |
aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> |
SH4: fix TMU init
Init the TMU and the ptimer with the correct cpu reset value
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel3
SH4: fix TMU init
Init the TMU and the ptimer with the correct cpu reset value
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6549 c046a42c-6fe2-441c-8c8c-71466251a162
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|
| #
5c16736a |
| 07-Dec-2008 |
balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> |
SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).
Main purpose of this is to delete
*physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This
SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).
Main purpose of this is to delete
*physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers.
But, IMHO, it is logically wrong.
Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have
one more address called A7 which is usually P4 address with upper 3bits masked.
This is an address only appears in TLB's physical address part.
Current code use trick writing drivers as if they are really in A7
(that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7.
Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
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|
| #
8da3ff18 |
| 01-Dec-2008 |
pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> |
Change MMIO callbacks to use offsets, not absolute addresses.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71
Change MMIO callbacks to use offsets, not absolute addresses.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162
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| #
96e2fc41 |
| 21-Nov-2008 |
aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> |
SH4: Use qemu_irq in timer emulation.
* hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source.
* hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init.
* hw/sh_intc.c (sh
SH4: Use qemu_irq in timer emulation.
* hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source.
* hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init.
* hw/sh_intc.c (sh_intc_set_irq): New.
(sh_intc_init): Allocate irqs.
* hw/sh_intc.h (struct intc_desc): New field irqs.
* hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source.
(sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source.
(sh_timer_init, tmu012_init): Adjust.
(Vladimir Prus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5768 c046a42c-6fe2-441c-8c8c-71466251a162
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| #
703243a0 |
| 12-Dec-2007 |
balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> |
Adds interrupt support to the sh specific timer code (Magnus Damm).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3812 c046a42c-6fe2-441c-8c8c-71466251a162
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| #
9596ebb7 |
| 18-Nov-2007 |
pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> |
Add statics and missing #includes for prototypes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3683 c046a42c-6fe2-441c-8c8c-71466251a162
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| #
87ecb68b |
| 17-Nov-2007 |
pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> |
Break up vl.h.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
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| #
cd1a3f68 |
| 29-Sep-2007 |
ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> |
Stand-alone TMU emulation code, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3269 c046a42c-6fe2-441c-8c8c-71466251a162
|