#
d7be40e1 |
| 15-Jul-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-tcg-20230715' of https://gitlab.com/rth7680/qemu into staging
tcg: Use HAVE_CMPXCHG128 instead of CONFIG_CMPXCHG128 accel/tcg: Introduce page_check_range_empty accel/tcg: Introduce p
Merge tag 'pull-tcg-20230715' of https://gitlab.com/rth7680/qemu into staging
tcg: Use HAVE_CMPXCHG128 instead of CONFIG_CMPXCHG128 accel/tcg: Introduce page_check_range_empty accel/tcg: Introduce page_find_range_empty accel/tcg: Accept more page flags in page_check_range accel/tcg: Return bool from page_check_range accel/tcg: Always lock pages before translation linux-user: Use abi_* types for target structures in syscall_defs.h linux-user: Fix abi_llong alignment for microblaze and nios2 linux-user: Fix do_shmat type errors linux-user: Implement execve without execveat linux-user: Make sure initial brk is aligned linux-user: Use a mask with strace flags linux-user: Implement MAP_FIXED_NOREPLACE linux-user: Widen target_mmap offset argument to off_t linux-user: Use page_find_range_empty for mmap_find_vma_reserved linux-user: Use 'last' instead of 'end' in target_mmap and subroutines linux-user: Remove can_passthrough_madvise linux-user: Simplify target_madvise linux-user: Drop uint and ulong types linux-user/arm: Do not allocate a commpage at all for M-profile CPUs bsd-user: Use page_check_range_empty for MAP_EXCL bsd-user: Use page_find_range_empty for mmap_find_vma_reserved
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSypEYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9VzQf/RMRK4SQDJiJEbQ6K # 5U1i955Rl4MMLT8PrkbT/UDA9soyIlSVjUenW8ThJJg6SLbSvkXZsWn165PFu+yW # nYkeCYxkJtAjWmmFlZ44J+VLEZZ6LkWrIvPZHvKohelpi6uT/fuQaAZjKuH2prI/ # 7bdP5YdLUMpCztERHYfxmroEX4wJR6knsRpt5rYchADxEfkWk82PanneCw7grQ6V # VNg1pRGplp0jMkpOOBvMD1ENkmoipklMe9P1gQdCHobg2/kqpozhT1oQp/gHNkP5 # 66Cjzv8o0nnPjJetm74pnP06iNhuMjDesD7f+Vq/DALgMobwjvhDW5GD+Ccto85B # hqvwHA== # =vm0t # -----END PGP SIGNATURE----- # gpg: Signature made Sat 15 Jul 2023 02:51:02 PM BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230715' of https://gitlab.com/rth7680/qemu: (47 commits) tcg: Use HAVE_CMPXCHG128 instead of CONFIG_CMPXCHG128 accel/tcg: Always lock pages before translation linux-user/arm: Do not allocate a commpage at all for M-profile CPUs linux-user: Drop uint and ulong linux-user: Simplify target_madvise linux-user: Remove can_passthrough_madvise accel/tcg: Return bool from page_check_range accel/tcg: Accept more page flags in page_check_range linux-user: Simplify target_munmap linux-user: Rename mmap_reserve to mmap_reserve_or_unmap linux-user: Rewrite mmap_reserve linux-user: Use 'last' instead of 'end' in target_mmap linux-user: Use page_find_range_empty for mmap_find_vma_reserved bsd-user: Use page_find_range_empty for mmap_find_vma_reserved accel/tcg: Introduce page_find_range_empty linux-user: Rewrite mmap_frag linux-user: Rewrite target_mprotect linux-user: Widen target_mmap offset argument to off_t linux-user: Split out target_to_host_prot linux-user: Implement MAP_FIXED_NOREPLACE ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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deba7870 |
| 06-Jul-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Always lock pages before translation
We had done this for user-mode by invoking page_protect within the translator loop. Extend this to handle system mode as well. Move page locking out
accel/tcg: Always lock pages before translation
We had done this for user-mode by invoking page_protect within the translator loop. Extend this to handle system mode as well. Move page locking out of tb_link_page.
Reported-by: Liren Wei <lrwei@bupt.edu.cn> Reported-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Richard W.M. Jones <rjones@redhat.com>
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4329d049 |
| 26-Jun-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-tcg-20230626' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Replace target_ulong in some APIs accel/tcg: Remove CONFIG_PROFILER accel/tcg: Store some tlb flags in CPUTLB
Merge tag 'pull-tcg-20230626' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Replace target_ulong in some APIs accel/tcg: Remove CONFIG_PROFILER accel/tcg: Store some tlb flags in CPUTLBEntryFull tcg: Issue memory barriers as required for the guest memory model tcg: Fix temporary variable in tcg_gen_gvec_andcs
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSZsPgdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+kWAf+ODI9qRvVbb4/uYv8 # k7wMhCxX9kk5bRVr+QcqDn9RekAdsyOKSdkAAv4NeRFqHs3ukxhMxu0N2aiVXGDw # WtpsV73FrivAXaCxRj0aaYCsX8qFUQM4eWORZX2+V4AO0BtMHx1loK3bUQwdBTqN # jgkpn8BYeFdfUJjvvEj9XeSJ7s0n/p7esaf6VKajef/PbrcgYAeHg72tb5Vv5LTI # oxhU4icpaq/FT+SolnGzh4nRV7yqji9qFJ2INb0Uanx/WxCMD6CQJ0rDw55UouvH # t7zGDn8FKDZJGQGxAbUav3evqWcBlkG5VzuhQli3P1+WbGF9jV0KI1nelOuafCKI # 0enECg== # =XvZb # -----END PGP SIGNATURE----- # gpg: Signature made Mon 26 Jun 2023 05:38:32 PM CEST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230626' of https://gitlab.com/rth7680/qemu: (22 commits) accel/tcg: Renumber TLB_DISCARD_WRITE accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK accel/tcg: Store some tlb flags in CPUTLBEntryFull accel/tcg: Remove check_tcg_memory_orders_compatible tcg: Add host memory barriers to cpu_ldst.h interfaces tcg: Do not elide memory barriers for !CF_PARALLEL in system mode target/microblaze: Define TCG_GUEST_DEFAULT_MO tcg: Fix temporary variable in tcg_gen_gvec_andcs accel/tcg: remove CONFIG_PROFILER tests/plugin: Remove duplicate insn log from libinsn.so softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr() accel/tcg: Replace target_ulong with vaddr in translator_*() accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup() accel: Replace target_ulong with vaddr in probe_*() accel/tcg: Widen pc to vaddr in CPUJumpCache accel/tcg/cpu-exec.c: Widen pc to vaddr accel/tcg/cputlb.c: Widen addr in MMULookupPageData accel/tcg/cputlb.c: Widen CPUTLBEntry access functions target: Widen pc/cs_base in cpu_get_tb_cpu_state ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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b1c09220 |
| 21-Jun-2023 |
Anton Johansson <anjo@rev.ng> |
accel/tcg: Replace target_ulong with vaddr in translator_*()
Use vaddr for guest virtual address in translator_use_goto_tb() and translator_loop().
Signed-off-by: Anton Johansson <anjo@rev.ng> Revi
accel/tcg: Replace target_ulong with vaddr in translator_*()
Use vaddr for guest virtual address in translator_use_goto_tb() and translator_loop().
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230621135633.1649-11-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
369081c4 |
| 05-Jun-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging
Build tcg/ once for system and once for user. Unmap perf_marker. Remove left over _link_error() definitions.
# -----BEG
Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging
Build tcg/ once for system and once for user. Unmap perf_marker. Remove left over _link_error() definitions.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmR+QekdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8NJwf+PE6ShfN+N65hwt0w # mgIrWNadgnXezEyaUdEuzLre9Ln9uD9Are948xIGPTVoLyr2wEr+Ma9dFI+GpTHY # 8C0b5v0SfHBBIK+wJb7VNcEdssRXVTcpikmmYv9IRpFTT8349bCdvJhuwojU5cyx # NGgq9ydJ/dEUDtmVU6EnOyLCDSHg2mc+KPVWhjXaVbVPTyP6Xmb0BwSSUt1t5NQK # Zw7E6G4z7QYXa7GNPTtXSWzTH3y9bSLQNj3jzHfJ6DPW23zxhFjCPhJYl1ecOHVF # pxXEEIjieHQxdlm3kg+tcCoZSJ6OXESNzu2D8zk8Kf6xJjMItTQOOuokWM6mBX4y # VbQoXg== # =8vrl # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 Jun 2023 01:13:29 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu: (52 commits) tcg/tcg-op-vec: Remove left over _link_error() definitions accel/tcg: Unmap perf_marker tcg: Build once for system and once for user-only exec/poison: Do not poison CONFIG_SOFTMMU plugins: Drop unused headers from exec/plugin-gen.h plugins: Move plugin_insn_append to translator.c tcg: Remove target-specific headers from tcg.[ch] tcg: Move env defines out of NEED_CPU_H in helper-head.h tcg: Fix PAGE/PROT confusion accel/tcg: Tidy includes for translator.[ch] target/arm: Add missing include of exec/exec-all.h target/*: Add missing includes of exec/translation-block.h target/mips: Tidy helpers for translation target/arm: Tidy helpers for translation accel/tcg: Move translator_fake_ldb out of line target/ppc: Inline gen_icount_io_start() accel/tcg: Introduce translator_io_start accel/tcg: Move most of gen-icount.h into translator.c include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE tcg: Spit out exec/translation-block.h ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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bc54ef8c |
| 02-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
plugins: Move plugin_insn_append to translator.c
This function is only used in translator.c, and uses a target-specific typedef: abi_ptr.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Sig
plugins: Move plugin_insn_append to translator.c
This function is only used in translator.c, and uses a target-specific typedef: abi_ptr.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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653c46da |
| 02-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Tidy includes for translator.[ch]
Reduce the header to only bswap.h and cpu_ldst.h. Move exec/translate-all.h to translator.c. Reduce tcg.h and tcg-op.h to tcg-op-common.h. Remove otherwi
accel/tcg: Tidy includes for translator.[ch]
Reduce the header to only bswap.h and cpu_ldst.h. Move exec/translate-all.h to translator.c. Reduce tcg.h and tcg-op.h to tcg-op-common.h. Remove otherwise unused headers.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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309e014d |
| 02-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Move translator_fake_ldb out of line
This is used by exactly one host in extraordinary circumstances. This means that translator.h need not include plugin-gen.h; translator.c already incl
accel/tcg: Move translator_fake_ldb out of line
This is used by exactly one host in extraordinary circumstances. This means that translator.h need not include plugin-gen.h; translator.c already includes plugin-gen.h.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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dfd1b812 |
| 23-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Introduce translator_io_start
New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h.
Revie
accel/tcg: Introduce translator_io_start
New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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56234233 |
| 02-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Move most of gen-icount.h into translator.c
The only usage of gen_tb_start and gen_tb_end are here. Move the static icount_start_insn variable into a local within translator_loop. Simpli
accel/tcg: Move most of gen-icount.h into translator.c
The only usage of gen_tb_start and gen_tb_end are here. Move the static icount_start_insn variable into a local within translator_loop. Simplify the two subroutines by passing in the existing local cflags variable.
Leave only the declaration of gen_io_start in gen-icount.h.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1c12355b |
| 24-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu into staging
util: Host cpu detection for x86 and aa64 util: Use cpu detection for bufferiszero migration: Use cpu detection for xb
Merge tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu into staging
util: Host cpu detection for x86 and aa64 util: Use cpu detection for bufferiszero migration: Use cpu detection for xbzrle tcg: Replace and remove cpu_atomic_{ld,st}o* host/include: Split qemu/atomic128.h tcg: Remove DEBUG_DISAS tcg: Remove USE_TCG_OPTIMIZATIONS
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRtbwAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8xlgf7B/RnVG7u7Hjndr6h # fH07ujjElAivs+H05S0GGbQYpSNlqVv8PzXT2olJTAe15ryb537dCkqxyKW53vgb # pUWzZf9Zy8XfN48W5V91dSKQE3gm5wBlOM6LI85F8XrIQyjZqkHti+rw3GxsamNL # 8n2euOR0vx/jculBRxvZUAJDzb/0shN583mC5+wX/KInCHiNmMC6sCggyd5bpFJZ # 1wqWwrUCqJ0KAAYKd9WrIKt6QwAX3kUDiBQPa1g+psBjZ1CYQ4lqZZn9uYQ4hEtG # yBnT0ER2LOBQaKXJ0BrdG5c/mUNX7WkLBDTb+QjGGkfPc/bHIirXqeFzuyrXahg8 # kY155w== # =XH8Z # -----END PGP SIGNATURE----- # gpg: Signature made Tue 23 May 2023 06:57:20 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu: (28 commits) tcg: Remove USE_TCG_OPTIMIZATIONS tcg: Remove DEBUG_DISAS qemu/atomic128: Add runtime test for FEAT_LSE2 qemu/atomic128: Improve cmpxchg fallback for atomic16_set tcg: Split out tcg/debug-assert.h accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc qemu/atomic128: Split atomic16_read accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128 accel/tcg: Remove prot argument to atomic_mmu_lookup accel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csst target/s390x: Use cpu_{ld,st}*_mmu in do_csst accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQ target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ include/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.h meson: Fix detect atomic128 support with optimization include/host: Split out atomic128-ldst.h include/host: Split out atomic128-cas.h util: Add cpuinfo-aarch64.c ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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645e3a81 |
| 01-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Remove DEBUG_DISAS
This had been set since the beginning, is never undefined, and it would seem to be harmful to debugging to do so.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Sig
tcg: Remove DEBUG_DISAS
This had been set since the beginning, is never undefined, and it would seem to be harmful to debugging to do so.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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f003dd8d |
| 06-Mar-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging
tcg: Merge two sequential labels accel/tcg: Retain prot flags from tlb_fill accel/tcg: Honor TLB_DISCARD_WRITE in atomic
Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging
tcg: Merge two sequential labels accel/tcg: Retain prot flags from tlb_fill accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup accel/tcg: Honor TLB_WATCHPOINTS in atomic_mmu_lookup target/sparc: Use tlb_set_page_full include/qemu/cpuid: Introduce xgetbv_low tcg/i386: Mark Win64 call-saved vector regs as reserved tcg: Decode the operand to INDEX_op_mb in dumps
Portion of the target/ patchset which eliminates use of tcg_temp_free* Portion of the target/ patchset which eliminates use of tcg_const*
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* tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu: (84 commits) target/xtensa: Avoid tcg_const_i32 target/xtensa: Split constant in bit shift target/xtensa: Use tcg_gen_subfi_i32 in translate_sll target/xtensa: Avoid tcg_const_i32 in translate_l32r target/xtensa: Tidy translate_clamps target/xtensa: Tidy translate_bb target/sparc: Avoid tcg_const_{tl,i32} target/s390x: Split out gen_ri2 target/riscv: Avoid tcg_const_* target/microblaze: Avoid tcg_const_* throughout target/i386: Simplify POPF target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign target/hexagon/idef-parser: Use gen_tmp for LPCFG target/hexagon: Use tcg_constant_* for gen_constant_from_imm docs/devel/tcg-ops: Drop recommendation to free temps tracing: remove transform.py include/exec/gen-icount: Drop tcg_temp_free in gen_tb_start target/tricore: Drop tcg_temp_free ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2a196de1 |
| 25-Feb-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Remove translator_loop_temp_check
Finish removing tcg temp free accounting interfaces.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.hen
accel/tcg: Remove translator_loop_temp_check
Finish removing tcg temp free accounting interfaces.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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2f2e911d |
| 25-Feb-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Remove tcg_check_temp_count, tcg_clear_temp_count
Since all temps allocated by guest front-ends are now TEMP_TB, and we don't recycle TEMP_TB, there's no point in requiring that the front-ends
tcg: Remove tcg_check_temp_count, tcg_clear_temp_count
Since all temps allocated by guest front-ends are now TEMP_TB, and we don't recycle TEMP_TB, there's no point in requiring that the front-ends free the temps at all. Begin by dropping the inner-most checks that all temps have been freed.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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a2b5f8b8 |
| 01-Mar-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into staging
helper-head: Add fpu/softfloat-types.h softmmu: Use memmove in flatview_write_continue tcg: Add sign param to probe_acce
Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into staging
helper-head: Add fpu/softfloat-types.h softmmu: Use memmove in flatview_write_continue tcg: Add sign param to probe_access_flags, probe_access_full tcg: Convert TARGET_TB_PCREL to CF_PCREL tcg: Simplify temporary lifetimes for translators
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmP/jWUdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9TcQf7B7+K/lrWvUVhZ4By # 7zrNIJKGwsxuQhGq9mS2Nx9ds9es5mS8SQT1ieNG6a51n6Gq8S2B8yFCRFdlDZWD # /QrMSjxrs+4c6pNHZu4v20Huy/VW0y004eYdGc8Lu5cXTDpy1mUZ2PrZYlWNQEVY # 4Ts5rTWdSZHRU1+dbB8MTWlml9//++TPB+ZvzqSb8jnRJfw4z7ijVJjUEEb93gQg # 8S3JiPU6d1ZzoXzGMK7Wd0MMi4pQUZkaX1HOpzvmQXjeErSP87CZvvji/Cucm8iW # rJ4U7t99nmZDqG9W1zdZfYfKNp4nLlfVldQWFVIx45awSPS0mCzrmeBT5NHyrxYK # 4OtuNQ== # =vzqE # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 Mar 2023 17:37:41 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu: (62 commits) tcg: Update docs/devel/tcg-ops.rst for temporary changes tcg: Remove tcg_temp_local_new_*, tcg_const_local_* exec/gen-icount: Don't use tcg_temp_local_new_i32 target/xtensa: Don't use tcg_temp_local_new_* target/ppc: Don't use tcg_temp_local_new target/mips: Don't use tcg_temp_local_new target/i386: Don't use tcg_temp_local_new target/hppa: Don't use tcg_temp_local_new target/hexagon/idef-parser: Drop gen_tmp_local target/hexagon: Don't use tcg_temp_local_new_* target/cris: Don't use tcg_temp_local_new target/arm: Don't use tcg_temp_local_new_* target/arm: Drop copies in gen_sve_{ldr,str} tcg: Change default temp lifetime to TEMP_TB tcg: Don't re-use TEMP_TB temporaries accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers accel/tcg/plugin: Use tcg_temp_ebb_* tcg: Use tcg_constant_ptr in do_dup tcg: Use tcg_temp_ebb_new_* in tcg/ tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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9b1890ad |
| 29-Jan-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Use more accurate max_insns for tb_overflow
Write back the number of insns that we attempt to translate, so that if we longjmp out we have a more accurate limit for the next attempt. Thi
accel/tcg: Use more accurate max_insns for tb_overflow
Write back the number of insns that we attempt to translate, so that if we longjmp out we have a more accurate limit for the next attempt. This results in fewer restarts when some limit is consumed by few instructions.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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597f9b2d |
| 29-Jan-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far.
Reviewed-by: Philip
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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526947e4 |
| 01-Mar-2023 |
Paolo Bonzini <pbonzini@redhat.com> |
Merge branch 'xenfv-kvm-15' of git://git.infradead.org/users/dwmw2/qemu into HEAD
This adds support for emulating Xen under Linux/KVM, based on kernel patches which have been present since Linux v5.
Merge branch 'xenfv-kvm-15' of git://git.infradead.org/users/dwmw2/qemu into HEAD
This adds support for emulating Xen under Linux/KVM, based on kernel patches which have been present since Linux v5.12. As with the kernel support, it's derived from work started by João Martins of Oracle in 2018.
This series just adds the basic platform support — CPUID, hypercalls, event channels, a stub of XenStore.
A full single-tenant internal implementation of XenStore, and patches to make QEMU's Xen PV drivers work with this Xen emulation, are waiting in the wings to be submitted in a follow-on patch series.
As noted in the documentation, it's enabled by setting the xen-version property on the KVM accelerator, e.g.:
qemu-system-x86_64 -serial mon:stdio -M q35 -display none -m 1G -smp 2 \ -accel kvm,xen-version=0x4000e,kernel-irqchip=split \ -kernel vmlinuz-6.0.7-301.fc37.x86_64 \ -append "console=ttyS0 root=/dev/sda1" \ -drive file=/var/lib/libvirt/images/fedora28.qcow2,if=none,id=disk \ -device ahci,id=ahci -device ide-hd,drive=disk,bus=ahci.0
Even before this was merged, we've already been using it to find and fix bugs in the Linux kernel Xen guest support:
https://lore.kernel.org/all/4bffa69a949bfdc92c4a18e5a1c3cbb3b94a0d32.camel@infradead.org/ https://lore.kernel.org/all/871qnunycr.ffs@tglx/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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62763403 |
| 28-Feb-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging
- buildsys - Various header cleaned up (removing pointless headers) - Mark various files/code user/system
Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging
- buildsys - Various header cleaned up (removing pointless headers) - Mark various files/code user/system specific - Make various objects target-independent - Remove tswapN() calls from dump.o - Suggest g_assert_not_reached() instead of assert(0)
- qdev / qom - Replace various container_of() by QOM cast macros - Declare some QOM macros using OBJECT_DECLARE_TYPE() - Embed OHCI QOM child in SM501 chipset
- hw (ISA & IDE) - add some documentation, improve function names - un-inline, open-code few functions - have ISA API accessing IRQ/DMA prefer ISABus over ISADevice - Demote IDE subsystem maintenance to "Odd Fixes"
- ui: Improve Ctrl+Alt hint on Darwin Cocoa
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* tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu: (125 commits) ui/cocoa: user friendly characters for release mouse dump: Add create_win_dump() stub for non-x86 targets dump: Simplify compiling win_dump.o by introducing win_dump_available() dump: Clean included headers dump: Replace TARGET_PAGE_SIZE -> qemu_target_page_size() dump: Replace tswapN() -> cpu_to_dumpN() hw/ide/pci: Add PCIIDEState::isa_irq[] hw/ide/via: Replace magic 2 value by ARRAY_SIZE / MAX_IDE_DEVS hw/ide/piix: Refactor pci_piix_init_ports as pci_piix_init_bus per bus hw/ide/piix: Pass Error* to pci_piix_init_ports() for better error msg hw/ide/piix: Remove unused includes hw/ide/pci: Unexport bmdma_active_if() hw/ide/ioport: Remove unnecessary includes hw/ide: Declare ide_get_[geometry/bios_chs_trans] in 'hw/ide/internal.h' hw/ide: Rename idebus_active_if() -> ide_bus_active_if() hw/ide: Rename ide_init2() -> ide_bus_init_output_irq() hw/ide: Rename ide_exec_cmd() -> ide_bus_exec_cmd() hw/ide: Rename ide_register_restart_cb -> ide_bus_register_restart_cb hw/ide: Rename ide_create_drive() -> ide_bus_create_drive() hw/ide: Rename ide_set_irq() -> ide_bus_set_irq() ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5b5968c4 |
| 19-Dec-2022 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
replay: Extract core API to 'exec/replay-core.h'
replay API is used deeply within TCG common code (common to user and system emulation). Unfortunately "sysemu/replay.h" requires some QAPI headers fo
replay: Extract core API to 'exec/replay-core.h'
replay API is used deeply within TCG common code (common to user and system emulation). Unfortunately "sysemu/replay.h" requires some QAPI headers for few system-specific declarations, example:
void replay_input_event(QemuConsole *src, InputEvent *evt);
Since commit c2651c0eaa ("qapi/meson: Restrict UI module to system emulation and tools") the QAPI header defining the InputEvent is not generated anymore. To keep it simple, extract the 'core' replay prototypes to a new "exec/replay-core.h" header which we include in the TCG code that doesn't need the rest of the replay API.
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <20221219170806.60580-5-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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#
ed9128c1 |
| 24-Feb-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230221' of https://gitlab.com/rth7680/qemu into staging
tcg: Allow first half of insn in ram, and second half in mmio linux-user/sparc: SIGILL for unknown trap vectors linux-us
Merge tag 'pull-tcg-20230221' of https://gitlab.com/rth7680/qemu into staging
tcg: Allow first half of insn in ram, and second half in mmio linux-user/sparc: SIGILL for unknown trap vectors linux-user/microblaze: SIGILL for privileged insns linux-user: Fix deadlock while exiting due to signal target/microblaze: Add gdbstub xml util: Adjust cacheflush for windows-arm64 include/sysemu/os-win32: Adjust setjmp/longjmp for windows-arm64
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* tag 'pull-tcg-20230221' of https://gitlab.com/rth7680/qemu: sysemu/os-win32: fix setjmp/longjmp on windows-arm64 util/cacheflush: fix cache on windows-arm64 target/microblaze: Add gdbstub xml linux-user/microblaze: Handle privileged exception cpus: Make {start,end}_exclusive() recursive linux-user: Always exit from exclusive state in fork_end() linux-user/sparc: Raise SIGILL for all unhandled software traps accel/tcg: Allow the second page of an instruction to be MMIO
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2627e452 |
| 06-Feb-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Allow the second page of an instruction to be MMIO
If an instruction straddles a page boundary, and the first page was ram, but the second page was MMIO, we would abort. Handle this as i
accel/tcg: Allow the second page of an instruction to be MMIO
If an instruction straddles a page boundary, and the first page was ram, but the second page was MMIO, we would abort. Handle this as if both pages are MMIO, by setting the ram_addr_t for the first page to -1.
Reported-by: Sid Manning <sidneym@quicinc.com> Reported-by: Jørgen Hansen <Jorgen.Hansen@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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f991d61d |
| 02-Feb-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-jan-omnibus-020223-1' of https://gitlab.com/stsquad/qemu into staging
Testing, docs, semihosting and plugin updates
- update playbooks for custom runners - add section timing su
Merge tag 'pull-jan-omnibus-020223-1' of https://gitlab.com/stsquad/qemu into staging
Testing, docs, semihosting and plugin updates
- update playbooks for custom runners - add section timing support to gitlab - upgrade fedora images to 37 - purge perl from the build system and deps - disable unstable tests in CI - improve intro, emulation and semihosting docs - semihosting bug fix and O_BINARY default - add memory-sve test - fix some races in qht - improve plugin handling of memory helpers - optimise plugin hooks - fix some plugin deadlocks - reduce win64-cross build time by dropping some targets
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmPb3fgACgkQ+9DbCVqe # KkQbXAf9Eoc+PdNvafbqzH/blPjvd9ve8pJ+GcPDukNXwxP8OF/jFEJUQ1E7l9O7 # y0qV4akKCdIqVice4R5bK2CAq44Y3aut8SDf56C8E3Riha2zA2RbQWOv/zCvA3OP # LFF+OaXZyg4JTR48HUKzh9ei2bd1+ccBSUe+xlRi59XaV5K8+5bmcZj10QKUR0lD # 0HC5auEWWpayvd5D7Da15C7+oVY3LMCFxSdpHwbuIPPan/TRo5yqMI6ChYDKB8QD # gdwMCL8znj2ADCTBftyBDYDAtjKVyLQidf7KdQHiSF+nmXYopS6SbsPCOMtJqCMH # tXcKAIxs/MEntPrWTKTdtdnzotJVKw== # =AtfN # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Feb 2023 15:59:52 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-jan-omnibus-020223-1' of https://gitlab.com/stsquad/qemu: (36 commits) gitlab: cut even more from cross-win64-system build plugins: Iterate on cb_lists in qemu_plugin_user_exit cpu-exec: assert that plugin_mem_cbs is NULL after execution tcg: exclude non-memory effecting helpers from instrumentation translator: always pair plugin_gen_insn_{start, end} calls plugins: fix optimization in plugin_gen_disable_mem_helpers plugins: make qemu_plugin_user_exit's locking order consistent with fork_start's util/qht: use striped locks under TSAN thread: de-const qemu_spin_destroy util/qht: add missing atomic_set(hashes[i]) cpu: free cpu->tb_jmp_cache with RCU tests/tcg: add memory-sve test for aarch64 semihosting: add O_BINARY flag in host_open for NT compatibility semihosting: Write back semihosting data before completion callback docs: add an introduction to the system docs semihosting: add semihosting section to the docs docs: add a new section to outline emulation support docs: add hotlinks to about preface text MAINTAINERS: Fix the entry for tests/tcg/nios2 gitlab: wrap up test results for custom runners ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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0f92d94a |
| 24-Jan-2023 |
Emilio Cota <cota@braap.org> |
translator: always pair plugin_gen_insn_{start, end} calls
Related: #1381
Signed-off-by: Emilio Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard He
translator: always pair plugin_gen_insn_{start, end} calls
Related: #1381
Signed-off-by: Emilio Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230108164731.61469-3-cota@braap.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230124180127.1881110-33-alex.bennee@linaro.org>
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