History log of /linux/include/dt-bindings/clock/nvidia,tegra264.h (Results 1 – 13 of 13)
Revision Date Author Comments
# cb9f145f 01-Nov-2025 Rob Clark <robin.clark@oss.qualcomm.com>

Merge remote-tracking branch 'drm/drm-next' into msm-next-robclark

Back-merge drm-next to get caught up.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>


# 8b87f67b 08-Oct-2025 Dmitry Torokhov <dmitry.torokhov@gmail.com>

Merge branch 'next' into for-linus

Prepare input updates for 6.18 merge window.


# f088104d 16-Sep-2025 Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Merge drm/drm-next into drm-intel-gt-next

Backmerge in order to get the commit:

048832a3f400 ("drm/i915: Refactor shmem_pwrite() to use kiocb and write_iter")

To drm-intel-gt-next as there are f

Merge drm/drm-next into drm-intel-gt-next

Backmerge in order to get the commit:

048832a3f400 ("drm/i915: Refactor shmem_pwrite() to use kiocb and write_iter")

To drm-intel-gt-next as there are followup fixes to be applied.

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

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# b4d90dbc 15-Sep-2025 Thomas Zimmermann <tzimmermann@suse.de>

Merge drm/drm-next into drm-misc-next-fixes

Backmerging to drm-misc-next-fixes to get features and fixes from
v6.17-rc6.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>


# 702fdf35 10-Sep-2025 Rodrigo Vivi <rodrigo.vivi@intel.com>

Merge drm/drm-next into drm-intel-next

Catching up with some display dependencies.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


# 4b051897 21-Aug-2025 Dmitry Torokhov <dmitry.torokhov@gmail.com>

Merge tag 'v6.17-rc2' into HEAD

Sync up with mainline to bring in changes to include/linux/sprintf.h


# ca994e89 12-Aug-2025 Lucas De Marchi <lucas.demarchi@intel.com>

Merge drm/drm-next into drm-xe-next

Bring v6.17-rc1 to propagate commits from other subsystems, particularly
PCI, which has some new functions needed for SR-IOV integration.

Signed-off-by: Lucas De

Merge drm/drm-next into drm-xe-next

Bring v6.17-rc1 to propagate commits from other subsystems, particularly
PCI, which has some new functions needed for SR-IOV integration.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

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# 8d2b0853 11-Aug-2025 Thomas Zimmermann <tzimmermann@suse.de>

Merge drm/drm-fixes into drm-misc-fixes

Updating drm-misc-fixes to the state of v6.17-rc1. Begins a new release
cycle.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>


# 08c51f5b 11-Aug-2025 Thomas Zimmermann <tzimmermann@suse.de>

Merge drm/drm-next into drm-misc-n

Updating drm-misc-next to the state of v6.17-rc1. Begins a new release
cycle.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>


# a53d0cf7 05-Aug-2025 Ingo Molnar <mingo@kernel.org>

Merge commit 'linus' into core/bugs, to resolve conflicts

Resolve conflicts with this commit that was developed in parallel
during the merge window:

8c8efa93db68 ("x86/bug: Add ARCH_WARN_ASM macro

Merge commit 'linus' into core/bugs, to resolve conflicts

Resolve conflicts with this commit that was developed in parallel
during the merge window:

8c8efa93db68 ("x86/bug: Add ARCH_WARN_ASM macro for BUG/WARN asm code sharing with Rust")

Conflicts:
arch/riscv/include/asm/bug.h
arch/x86/include/asm/bug.h

Signed-off-by: Ingo Molnar <mingo@kernel.org>

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# 115e74a2 29-Jul-2025 Linus Torvalds <torvalds@linux-foundation.org>

Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC devicetree updates from Arnd Bergmann:
"There are a few new variants of existing chips:

- mt6572 is an

Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC devicetree updates from Arnd Bergmann:
"There are a few new variants of existing chips:

- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now

- exynos2200 is a recent high-end mobile phone chip used in a few
Samsung phones like the Galaxy S22

- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications

- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it

There are five more chips in a separate branch, as those are new chip
families that I merged along with the necessary infrastructure.

New board support is not that exciting, with a total of 33 newly added
machines here:

- Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
sg2042

- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95

- Two newly added ASPEED BMC based motherboards, and one that got
removed

- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs

- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1

- A set-top box based on Amlogic meson-gxm

Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5"

* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
riscv: dts: sophgo: fix mdio node name for CV180X
riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
riscv: dts: sophgo: add ethernet GMAC device for sg2042
riscv: dts: sophgo: Enable ethernet device for Huashan Pi
riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
riscv: dts: sophgo: Add ethernet device for cv18xx
riscv: dts: sophgo: sg2044: add pmu configuration
riscv: dts: sophgo: sg2044: add ziccrse extension
riscv: dts: sophgo: add zfh for sg2042
riscv: dts: sophgo: add ziccrse for sg2042
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
riscv: dts: sophgo: sg2044: add MSI device support for SG2044
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
...

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# 8fa90d09 22-Jul-2025 Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

dt-bindings: Updates for v6.17-rc1

Add Tegra264 compatible strings for some core co

Merge tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

dt-bindings: Updates for v6.17-rc1

Add Tegra264 compatible strings for some core components and extend
bindings where necessary to accomodate the new hardware generation. Also
document some new platforms, for both old and new chips.

* tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: arm: tegra: Add Asus Portable AiO P1801-T
dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T
dt-bindings: Add Tegra264 clock and reset definitions
dt-bindings: tegra: Document P3971-0089+P3834-0008 Platform
dt-bindings: rtc: tegra: Document Tegra264 RTC
dt-bindings: dma: Add Tegra264 compatible string
dt-bindings: misc: Document Tegra264 APBMISC compatible
dt-bindings: firmware: Document Tegra264 BPMP
dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list
dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
dt-bindings: tegra: pmc: Add Tegra264 compatible
dt-bindings: memory: tegra: Add Tegra264 support

Link: https://lore.kernel.org/r/20250711220943.2389322-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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# 319cc06d 08-Jul-2025 Thierry Reding <treding@nvidia.com>

dt-bindings: Add Tegra264 clock and reset definitions

The BPMP firmware on Tegra264 defines a set of IDs for clock and reset
resources. These are not enumerations but provided by hardware, and 0 is

dt-bindings: Add Tegra264 clock and reset definitions

The BPMP firmware on Tegra264 defines a set of IDs for clock and reset
resources. These are not enumerations but provided by hardware, and 0 is
a reserved value, hence the numbering starts at 1.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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