clk: samsung: Pass mask to wait_until_mux_stable()

Make it possible to use wait_until_mux_stable() for MUX registers where
the mask is different from MUX_MASK (e.g. in upcoming CPU clock
implementat

clk: samsung: Pass mask to wait_until_mux_stable()

Make it possible to use wait_until_mux_stable() for MUX registers where
the mask is different from MUX_MASK (e.g. in upcoming CPU clock
implementation for Exynos850).

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-12-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

show more ...

clk: samsung: Keep register offsets in chip specific structure

Abstract CPU clock registers by keeping their offsets in a dedicated
chip specific structure to accommodate for oncoming Exynos850 supp

clk: samsung: Keep register offsets in chip specific structure

Abstract CPU clock registers by keeping their offsets in a dedicated
chip specific structure to accommodate for oncoming Exynos850 support,
which has different offsets for cluster 0 and cluster 1. This rework
also makes it possible to use exynos_set_safe_div() for all chips, so
exynos5433_set_safe_div() is removed here to reduce the code
duplication. The ".regs" field has to be (void *) as different Exynos
chips can have very different register layout, so this way it's possible
for ".regs" to point to different structures, each representing its own
chip's layout.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-11-semen.protsenko@linaro.org
[krzysztof: drop redundant const for regs in exynos_cpuclk_chip]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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clk: samsung: Keep CPU clock chip specific data in a dedicated struct

Keep chip specific data in the data structure, don't mix it with code.
It makes it easier to add more chip specific data further

clk: samsung: Keep CPU clock chip specific data in a dedicated struct

Keep chip specific data in the data structure, don't mix it with code.
It makes it easier to add more chip specific data further. Having all
chip specific data in the table eliminates possible code bloat when
adding more rate handlers for new chips, and also makes it possible to
keep some other chip related data in that array.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-10-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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clk: samsung: Pass register layout type explicitly to CLK_CPU()

Use a dedicated enum field to explicitly specify which register layout
should be used for the CPU clock, instead of passing it as a bi

clk: samsung: Pass register layout type explicitly to CLK_CPU()

Use a dedicated enum field to explicitly specify which register layout
should be used for the CPU clock, instead of passing it as a bit flag.
This way it would be possible to keep the chip-specific data in some
array, where each chip structure could be accessed by its corresponding
layout index. It prepares clk-cpu.c for adding new chips support, which
might have different data for different CPU clusters.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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clk: samsung: Pass actual CPU clock registers base to CPU_CLK()

The documentation for struct exynos_cpuclk says .ctrl_base field should
contain the controller base address. There are two different p

clk: samsung: Pass actual CPU clock registers base to CPU_CLK()

The documentation for struct exynos_cpuclk says .ctrl_base field should
contain the controller base address. There are two different problems
with that:

1. All Exynos clock drivers are actually passing CPU_SRC register offset
via CPU_CLK() macro, which in turn gets assigned to mentioned
.ctrl_base field. Because CPU_SRC register usually already has 0x200
offset from controller's base, all other register offsets in
clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC
offset, and not from controller's base. That makes things confusing
and inconsistent with register offsets provided in Exynos clock
drivers, also breaking the contract for .ctrl_base field as described
in struct exynos_cpuclk doc.

2. Furthermore, some Exynos chips have an additional offset for the
start of CPU clock registers block (inside of the CMU). There might
be different reasons for that, e.g.:

- The CMU contains clocks for two different CPUs (like in Exynos5420)
- The CMU contains also non-CPU clocks as well (like in Exynos4)
- The CPU CMU exists as a dedicated hardware block in the SoC layout,
but is modelled as a part of bigger CMU in the driver (like in case
of Exynos3250)

That means the .ctrl_base field is actually not a controller's base,
but instead it's a start address of the CPU clock registers inside of
the CMU.

Rework all register offsets in clk-cpu.c to be actual offsets from the
CPU clock register block start, and fix offsets provided to CPU_CLK()
macro in all Exynos clock drivers. Also clarify the .ctrl_base field
documentation and rename it to just .base, because it doesn't really
contain the CMU base.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-8-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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clk: samsung: Group CPU clock functions by chip

clk-cpu.c is going to get messy as new chips support is added.
Restructure the code by pulling related functions and definitions
together, grouping th

clk: samsung: Group CPU clock functions by chip

clk-cpu.c is going to get messy as new chips support is added.
Restructure the code by pulling related functions and definitions
together, grouping those by their relation to a particular chip or other
categories, to simplify the code navigation.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-7-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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clk: samsung: Use single CPU clock notifier callback for all chips

Reduce the code duplication by making all chips use a single version of
exynos_cpuclk_notifier_cb() function. That will prevent the

clk: samsung: Use single CPU clock notifier callback for all chips

Reduce the code duplication by making all chips use a single version of
exynos_cpuclk_notifier_cb() function. That will prevent the code bloat
when adding new chips support too.

Also don't pass base address to pre/post rate change functions, as it
can be easily derived from already passed cpuclk param.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-6-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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clk: samsung: Reduce params count in exynos_register_cpu_clock()

Pass CPU clock data structure to exynos_register_cpu_clock() instead of
passing its fields separately there. That simplifies the sign

clk: samsung: Reduce params count in exynos_register_cpu_clock()

Pass CPU clock data structure to exynos_register_cpu_clock() instead of
passing its fields separately there. That simplifies the signature of
exynos_register_cpu_clock() and makes it easier to add more fields to
struct samsung_cpu_clock later. This style follows the example of
samsung_clk_register_pll().

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-5-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

show more ...

clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c

Reduce the scope of struct exynos_cpuclk, as it's only used in clk-cpu.c
internally. All drivers using clk-pll.h already include clk.h as well,

clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c

Reduce the scope of struct exynos_cpuclk, as it's only used in clk-cpu.c
internally. All drivers using clk-pll.h already include clk.h as well,
so this change doesn't break anything.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

show more ...

clk: samsung: Improve clk-cpu.c style

clk-cpu.c has numerous style issues reported by checkpatch and easily
identified otherwise. Give it some love and fix those warnings where it
makes sense. Also

clk: samsung: Improve clk-cpu.c style

clk-cpu.c has numerous style issues reported by checkpatch and easily
identified otherwise. Give it some love and fix those warnings where it
makes sense. Also make stabilization time a named constant to get rid of
the magic number in clk-cpu.c.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-3-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

show more ...

Merge branch 'next' into for-linus

Prepare input updates for 6.12 merge window.

Merge branch 'ib/6.11-rc6-matrix-keypad-spitz' into next

Bring in changes removing support for platform data from matrix-keypad
driver.

Merge drm/drm-next into drm-xe-next

Get drm-xe-next on v6.11-rc2 and synchronized with drm-intel-next for
the display side. This resolves the current conflict for the
enable_display module parameter

Merge drm/drm-next into drm-xe-next

Get drm-xe-next on v6.11-rc2 and synchronized with drm-intel-next for
the display side. This resolves the current conflict for the
enable_display module parameter and allows further pending refactors.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

show more ...

Merge tag 'v6.11-rc3' into trace/ring-buffer/core

The "reserve_mem" kernel command line parameter has been pulled into
v6.11. Merge the latest -rc3 to allow the persistent ring buffer memory to
be a

Merge tag 'v6.11-rc3' into trace/ring-buffer/core

The "reserve_mem" kernel command line parameter has been pulled into
v6.11. Merge the latest -rc3 to allow the persistent ring buffer memory to
be able to be mapped at the address specified by the "reserve_mem" command
line parameter.

Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>

show more ...

Merge drm/drm-next into drm-misc-next

Get drm-misc-next to the state of v6.11-rc2.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge branch 'linus' into x86/mm

Bring x86 and selftests up to date

Merge drm/drm-next into drm-intel-next

Sync with v6.11-rc1 in general, and specifically get the new
BACKLIGHT_POWER_ constants for power states.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Merge tag 'v6.11-rc1' into for-6.12

Linux 6.11-rc1

Merge drm/drm-fixes into drm-misc-fixes

Let's start the new drm-misc-fixes cycle by bringing in 6.11-rc1.

Signed-off-by: Maxime Ripard <mripard@kernel.org>

Merge tag 'v6.11-rc1' into clk-meson-next

Linux 6.11-rc1

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This a large collection of clk driver updates and a handful of new SoC
cl

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This a large collection of clk driver updates and a handful of new SoC
clk driver support.

We have the usual Qualcomm clk drivers, along with clk drivers for the
Sophgo and T-Head vendors, all to support some new SoCs.

Nothing in particular stands out to me in the updates. There's the
interconnect clk driver which exposes clks as interconnects, crossing
subsystems. There's a bunch of janitorial things that are improving
drivers in general like kmemdup_array() or fixing error paths. But
overall the updates look normal to fix the description data which is
usually the stuff that's wrong and/or untested.

Core:
- Skip gate basic type KUnit tests on s390 due to lack of MMIO
emulation

New Drivers:
- AP sub-system clock controller in the T-Head TH1520
- Sophgo Sophon sg2042 clk driver
- Qualcomm SM7150 camera, display and video clk drivers
- Qualcomm QCM2290 GPU clk driver
- Qualcomm QCS8386/QCS8084 NSS clk driver
- Qualcomm SM8650 camera and video drivers

Updates:
- Add reset support to Airoha EN7581 clk driver
- Add MODULE_DESCRIPTIONs to various clk drivers
- Introduce helper logic to expose clock controllers as simple
interconnect providers
- Use the interconnect helper above on Qualcomm ipq9574
- Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on
Qualcomm X1Elite
- Improve error handling in Qualcomm kpss-xcc driver
- Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
- Export more clocks for Rockchip rk3128 peripherals
- Convert Rockchip clk drivers to use kmemdup_array()
- Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
- Make qcom_cc_really_probe() take a struct device to allow reuse in
non-platform-drivers
- Introduce prepare-only branch clock ops in the qcom clk driver to
support clocks on buses that take locks
- Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
- Support Qualcomm Huayra 2290 alpha PLL
- Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to
match HS200 support
- Add missing PCIe PIPE clocks on Qualcomm IPQ9574
- Fix various configurations and properties in the Qualcomm SA8775P,
X1E80100 and SM7280 drivers
- Park Qualcomm SM8350 GPU RCGs on XO while disabled
- Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
- exynos-clkout: Remove usage of of_device_id table as
.of_match_table, because the driver is instantiated as MFD cell,
not as standalone platform driver. Populated .of_match_table
confused people few times to convert the code to
device_get_match_data(), which broke the driver
- Mark one Samsung UFS clock as critical, because having it off stops
the system from shutdown
- Use kmemdup_array() when applicable
- Remove unused 'struct gates_data' from old sunxi driver library
- Add GPADC clock and reset for Allwinner H616
- Minor Amlogic S4 clock fixes
- DT bindings Yaml conversion of the Amlogic AXG audio controller
- Amlogic C3 clock controllers support
- Amlogic clk flag added to skip init of already enabled PLLs and
avoid relocking
- Amlogic A1 DT bindings updates for system pll support
- Add missing MODULE_DESCRIPTION where necessary
- Remove obsolete clock DT binding header files
- Add Battery Backup (VBATTB) and I2C clocks, resets, and power
domains on Renesas RZ/G3S
- Add audio clocks on Renesas R-Car V4M
- Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
clk: sunxi-ng r40: Constify struct regmap_config
clk: en7523: fix rate divider for slic and spi clocks
clk: lpc32xx: Constify struct regmap_config
clk: xilinx: Constify struct regmap_config
clk: en7523: Remove PCIe reset open drain configuration for EN7581
clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
clk: en7523: Add reset-controller support for EN7581 SoC
dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
dt-bindings: clock: sprd,sc9860-clk: convert to YAML
dt-bindings: clock: qoriq-clock: convert to yaml format
clk: qcom: Park shared RCGs upon registration
clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
...

show more ...

Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-samsung' into clk-next

* clk-renesas:
clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
clk: renesa

Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-samsung' into clk-next

* clk-renesas:
clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
clk: renesas: r8a779h0: Add Audio clocks
clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
dt-bindings: clock: rcar-gen2: Remove obsolete header files
dt-bindings: clock: r8a7779: Remove duplicate newline
clk: renesas: Drop "Renesas" from individual driver descriptions
clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments
clk: renesas: r8a779h0: Add VIN clocks
dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells
clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock
clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
clk: renesas: r8a77970: Use common cpg_lock
clk: renesas: r8a779h0: Add CSI-2 clocks
clk: renesas: r8a779h0: Add ISPCS clocks

* clk-amlogic:
clk: meson: add missing MODULE_DESCRIPTION() macros
dt-bindings: clock: meson: a1: peripherals: support sys_pll input
dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL
clk: meson: c3: add c3 clock peripherals controller driver
clk: meson: c3: add support for the C3 SoC PLL clock
dt-bindings: clock: add Amlogic C3 peripherals clock controller
dt-bindings: clock: add Amlogic C3 SCMI clock controller support
dt-bindings: clock: add Amlogic C3 PLL clock controller
dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format
clk: meson: s4: fix pwm_j_div parent clock
clk: meson: s4: fix fixed_pll_dco clock

* clk-allwinner:
clk: sunxi-ng r40: Constify struct regmap_config
clk: sunxi-ng: h616: Add clock/reset for GPADC
dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks
clk: sunxi: Remove unused struct 'gates_data'
clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros

* clk-samsung:
clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical
clk: samsung: Switch to use kmemdup_array()
clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE

show more ...

Merge branch 'next' into for-linus

Prepare input updates for 6.11 merge window.

Merge tag 'samsung-clk-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clk drivers updates from Krzysztof Kozlowski:

- exynos-clkout: Remove u

Merge tag 'samsung-clk-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clk drivers updates from Krzysztof Kozlowski:

- exynos-clkout: Remove usage of of_device_id table as .of_match_table,
because the driver is instantiated as MFD cell, not as standalone
platform driver. Populated .of_match_table confused people few times
to convert the code to device_get_match_data(), which broke the
driver.
- Mark one of UFS clocks as critical, because having it off stops the
system from shutdown
- Use kmemdup_array() when applicable

* tag 'samsung-clk-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical
clk: samsung: Switch to use kmemdup_array()
clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE

show more ...

clk: samsung: Switch to use kmemdup_array()

Let the kememdup_array() take care about multiplication and possible
overflows.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link:

clk: samsung: Switch to use kmemdup_array()

Let the kememdup_array() take care about multiplication and possible
overflows.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20240606161028.2986587-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

show more ...