x86: access: add PKE testcases

Tested with TCG so far.

access.c could stand a rewrite, but for now this will do.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

x86: eventinj: make test work with -O0

With optimizations disabled, the compiler generated a call for
irq_enable() -- rather than just inlining an sti instruction as
expected. Thus the irq_enable re

x86: eventinj: make test work with -O0

With optimizations disabled, the compiler generated a call for
irq_enable() -- rather than just inlining an sti instruction as
expected. Thus the irq_enable ret would run in the sti shadow and the
vectors would fire in the wrong order.

Signed-off-by: Peter Feiner <pfeiner@google.com>
Message-Id: <1456967378-6367-5-git-send-email-pfeiner@google.com>
[Add comment to irq_enable. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: vmx: fix definition of X86_CR4_VMXE

Was defined as 0x1 when it should have been 0x2000 (13th bit of CR4).
See Intel manual 23.7. 0x1 is the VME 'Virtual-8086 Mode Extensions'
bit, which the vmx

x86: vmx: fix definition of X86_CR4_VMXE

Was defined as 0x1 when it should have been 0x2000 (13th bit of CR4).
See Intel manual 23.7. 0x1 is the VME 'Virtual-8086 Mode Extensions'
bit, which the vmx tests don't exercise.

The correct bit was being set thanks to IA32_VMX_CR4_FIXED{0,1} MSRs
forcing it.

I hacked the test setup to forcibly un-set the bit and observed the
correct #UD VMXON behavior. Adding a test to verify the #UD behavior
is follow-up work.

Signed-off-by: Peter Feiner <pfeiner@google.com>
Message-Id: <1456184436-31168-1-git-send-email-pfeiner@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: use asm volatile for flags and segment register read/writes

The effects of a move from or to these registers is not entirely described
by the asm's operands. Therefore, it may happen that the

x86: use asm volatile for flags and segment register read/writes

The effects of a move from or to these registers is not entirely described
by the asm's operands. Therefore, it may happen that the compiler
moves the asm around in ways that break tests.

In one case, the compiler marked read_ss() as pure and thus subjected
it to common subexpression elimination:

u16 ss = read_ss();

// check for null segment load
*mem = 0;
asm volatile("mov %0, %%ss" : : "m"(*mem));
report("mov null, %%ss", read_ss() == 0);

This caused a spurious failure of the test.

Reported-by: Lucas Meneguel Rodrigues <lmr@scylladb.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: pkeys: add test for PKEYS

Signed-off-by: Huaitong Han <huaitong.han@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

KVM: x86: a few more x86-specific functions

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

x86: tsc: add test for RDTSCP

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

x86: Check level, xlevel before returning CPUID data

None of the existing code using cpuid checks level or xlevel before
running it. Instead of changing all callers, make the cpuid() function
check

x86: Check level, xlevel before returning CPUID data

None of the existing code using cpuid checks level or xlevel before
running it. Instead of changing all callers, make the cpuid() function
check if the requested leaf is available, before returning any data.

All existing callers of cpuid() and cpuid_indexed() are checks for the
presence of feature bits, so it is safe to return all zeroes when the
requested CPUID leaf is not available.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: apic: Look up MAXPHYADDR on CPUID correctly

When the CPUID xlevel on QEMU is < 0x80000008, we get the following:

$ ./x86-run x86/apic.flat -smp 2 -cpu qemu64,xlevel=0x80000007
[...]

x86: apic: Look up MAXPHYADDR on CPUID correctly

When the CPUID xlevel on QEMU is < 0x80000008, we get the following:

$ ./x86-run x86/apic.flat -smp 2 -cpu qemu64,xlevel=0x80000007
[...]
FAIL: apicbase: reserved physaddr bits

That happens because CPUID[0x80000008].EAX won't have the expected data
if xlevel < 0x80000008.

When the CPUID physical address bits information is not available on CPUID,
assume it is 36, as documented on Intel SDM, Volume 3A, section
10.4.4 "Local APIC Status and Location":

> Bits 0 through 7, bits 9 and 10, and bits MAXPHYADDR[1] through 63 in the
> IA32_APIC_BASE MSR are reserved.
>
> [1] The MAXPHYADDR is 36 bits for processors that do not support CPUID
> leaf 80000008H, or indicated by CPUID.80000008H:EAX[bits 7:0] for
> processors that support CPUID leaf 80000008H."

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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VMX: move write_rflags inside asm blocks for vmx instructions

This makes sure that the flags register doesn't get accidentally
overwritten due to compiler optimizations or other means

Signed-off-by

VMX: move write_rflags inside asm blocks for vmx instructions

This makes sure that the flags register doesn't get accidentally
overwritten due to compiler optimizations or other means

Signed-off-by: Bandan Das <bsd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: smap: new testcase

Test various combinations of the AC bit and reading/writing into
user pages at CPL=0.

One notable missing test is implicit kernel reads and writes (e.g.
reading the IDT/GDT/

x86: smap: new testcase

Test various combinations of the AC bit and reading/writing into
user pages at CPL=0.

One notable missing test is implicit kernel reads and writes (e.g.
reading the IDT/GDT/LDT/TSS). The interesting part of this is that
AC must be ignored in ring 3; the processor always behaves as if AC=0.
I skipped this because QEMU doesn't emulate this correctly, and because
right now there's no kvm-unit-tests infrastructure to run code in ring
3 at all.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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x86: move CR0 and CR4 constants to processor.h

Move them together with the inline function that read/write the
control registers.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

x86: move size #defines to processor.h

These are necessary in many testcases that includes hand-written
assembly, otherwise they will only run for either 32- or 64-bit.

Signed-off-by: Paolo Bonzini

x86: move size #defines to processor.h

These are necessary in many testcases that includes hand-written
assembly, otherwise they will only run for either 32- or 64-bit.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Remove duplicate read_rflags() definition.

Signed-off-by: Gleb Natapov <gleb@redhat.com>

Test fault during IRET from NMI.

This test checks that NMI window opens only after IRET from NMI is
executed without a fault.

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Na

Test fault during IRET from NMI.

This test checks that NMI window opens only after IRET from NMI is
executed without a fault.

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>

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kvm-unit-tests : Basic architecture of VMX nested test case

This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
V

kvm-unit-tests : Basic architecture of VMX nested test case

This is the first version of VMX nested environment. It contains the
basic VMX instructions test cases, including VMXON/VMXOFF/VMXPTRLD/
VMXPTRST/VMCLEAR/VMLAUNCH/VMRESUME/VMCALL. This patchalso tests the
basic execution routine in VMX nested environment andlet the VM print
"Hello World" to inform its successfully run.

The first release also includes a test suite for vmenter (vmlaunch and
vmresume). Besides, hypercall mechanism is included and currently it is
used to invoke VM normal exit.

New files added:
x86/vmx.h : contains all VMX related macro declerations
x86/vmx.c : main file for VMX nested test case

Signed-off-by: Arthur Chunqi Li <yzt356@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Add async page fault test

The test checks that when hypervisor prefaults swapped in page it does
not generates spurious #PFs in case page was unmapped while it was
swapped out.

Signed-off-by: Marce

Add async page fault test

The test checks that when hypervisor prefaults swapped in page it does
not generates spurious #PFs in case page was unmapped while it was
swapped out.

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>

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Add rdpmc instruction accessor

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>

Move invlpg() into library code

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>

Move irq_(enable|disable) into library code

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>

Change LTR's operand to be a u16

This makes it pick the correct register size.

Signed-off-by: Avi Kivity <avi@redhat.com>

Export tsc related helpers

Signed-off-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>

Initial commit from qemu-kvm.git kvm/test/

Signed-off-by: Avi Kivity <avi@redhat.com>