5b929cb2 | 26-Jan-2025 |
Jinank Jain <jinankjain@microsoft.com> |
hypervisor: Implement hypervisor agnostic variant of VcpuInit
This will help in fixing the build issue for MSHV on ARM64.
Signed-off-by: Jinank Jain <jinankjain@microsoft.com> |
ee0b0d43 | 15-Jan-2025 |
Jinank Jain <jinankjain@microsoft.com> |
hypervisor: Implement hypervisor agnostic variant of RegList
This helps in unification of RegList across different platforms.
Signed-off-by: Jinank Jain <jinankjain@microsoft.com> |
06148234 | 15-Jan-2025 |
Jinank Jain <jinankjain@microsoft.com> |
hypervisor: Implement hypervisor agnostic Register interface
This will help in fixing the build issue for MSHV on ARM64.
Signed-off-by: Jinank Jain <jinankjain@microsoft.com> |
7db3002e | 05-Feb-2025 |
Jinank Jain <jinankjain@microsoft.com> |
build: Bump mshv crate to latest version
Move mshv crates from v0.3.2 to v0.3.3
Signed-off-by: Jinank Jain <jinankjain@microsoft.com> |
3509b5bf | 21-Jan-2025 |
Ruoqing He <heruoqing@iscas.ac.cn> |
hypervisor: Create vcpu before initialize AIA
Create a corresponding `vcpu` in `test_create_aia` to capture wrongly configured RISC-V IMSIC attr.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn> |
cf463b88 | 21-Jan-2025 |
Ruoqing He <heruoqing@iscas.ac.cn> |
hypervisor: Fix AIA IMSIC attr calculation
The IMSIC attr of RISC-V AIA is wrongly configured to start from 0, which would error out with `os error 22` (invalid argument).
```console Error booting
hypervisor: Fix AIA IMSIC attr calculation
The IMSIC attr of RISC-V AIA is wrongly configured to start from 0, which would error out with `os error 22` (invalid argument).
```console Error booting VM: VmBoot(DeviceManager(CreateInterruptController(CreateAia(CreateVaia(Vaia error SetDeviceAttribute(SetDeviceAttribute(Invalid argument (os error 22)))))))) ```
`riscv_imsic_attr_of` should shift `cpu_index` by 1 here to produce correct IMSIC attr.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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293cf90e | 13-Jan-2025 |
Rob Bradford <rbradford@rivosinc.com> |
hypervisor: Implement fmt::Display for CpuIdEntry
Signed-off-by: Rob Bradford <rbradford@rivosinc.com> |
5b42aa0b | 09-Jan-2025 |
Wei Liu <liuwe@microsoft.com> |
hypervisor: kvm: fix an operator precedence clippy warning
Signed-off-by: Wei Liu <liuwe@microsoft.com> |
a322e2d6 | 06-Jan-2025 |
Rob Bradford <rbradford@rivosinc.com> |
hypervisor: Automatically fix operator precedence clippy warning
Signed-off-by: Rob Bradford <rbradford@rivosinc.com> |
fe24a7a2 | 02-Jan-2025 |
Wei Liu <liuwe@microsoft.com> |
hypervisor: introduce an mshv_emulator feature
This will become useful when we build the fuzzing target for the instruction emulator, because there is no need to pull in the rest of the hypervisor c
hypervisor: introduce an mshv_emulator feature
This will become useful when we build the fuzzing target for the instruction emulator, because there is no need to pull in the rest of the hypervisor crate in that situation.
Signed-off-by: Wei Liu <liuwe@microsoft.com>
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73e1451a | 02-Jan-2025 |
Wei Liu <liuwe@microsoft.com> |
hypervisor: emulator: use wrapping arithmetic
Signed-off-by: Wei Liu <liuwe@microsoft.com> |
1180f757 | 02-Jan-2025 |
Wei Liu <liuwe@microsoft.com> |
hypervisor: emulator: adjust iced-x86 feature flags
The fastfmt feature and VEX support use techniques that appear to leak memory in the eye of LLVM's address sanitizer.
While at it, disable a bunc
hypervisor: emulator: adjust iced-x86 feature flags
The fastfmt feature and VEX support use techniques that appear to leak memory in the eye of LLVM's address sanitizer.
While at it, disable a bunch of instruction set decoding support we never intend to support.
Signed-off-by: Wei Liu <liuwe@microsoft.com>
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4e298d1a | 05-Sep-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: maintain a bitmap for SEV-SNP VM on MSHV
Add a bitmap to MshvVM struct for caching the pages that the VMM got shared access from the guest.
Signed-off-by: Muminul Islam <muislam@microso
hypervisor: maintain a bitmap for SEV-SNP VM on MSHV
Add a bitmap to MshvVM struct for caching the pages that the VMM got shared access from the guest.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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4054a49e | 05-Sep-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: use memory size during VM creation
For SEV-SNP VM on MSHV we need to request page access during IO, we want to avoid such request for the page that have already been requested. In order
hypervisor: use memory size during VM creation
For SEV-SNP VM on MSHV we need to request page access during IO, we want to avoid such request for the page that have already been requested. In order to maintain the bitmap we need the memory size during bitmap creation.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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e4a5219f | 07-Nov-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: mshv: modify GuestRequest handling for CVM
VMM needs to handle VMG exit for guest request. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expen
hypervisor: mshv: modify GuestRequest handling for CVM
VMM needs to handle VMG exit for guest request. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expensive and update the GHCB page using mapped(root partition) struct.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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a458351d | 07-Nov-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: mshv: modify MMIO exit handling for CVM
VMM needs to handle VMG exit for MMIO. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expensive and upd
hypervisor: mshv: modify MMIO exit handling for CVM
VMM needs to handle VMG exit for MMIO. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expensive and update the GHCB page using mapped(root partition) struct.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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5a27bf87 | 07-Nov-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: mshv: modify IoPort handling for CVM
VMM needs to handle VMG exit for IO Port. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expensive and upd
hypervisor: mshv: modify IoPort handling for CVM
VMM needs to handle VMG exit for IO Port. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expensive and update the GHCB page using mapped(root partition) struct.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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310dafb4 | 07-Nov-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: mshv: modify doorbell page handling for CVM
VMM needs to handle VMG exit for doorbell page. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expe
hypervisor: mshv: modify doorbell page handling for CVM
VMM needs to handle VMG exit for doorbell page. This patch removes the old method that uses gpa_read/write(IOCTL and hypercall), which is expensive and update the GHCB page using mapped(root partition) struct.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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78895dcc | 25-Oct-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: mshv: clear exitinfo1 using mapped ghcb address
After handling the VMG exit vmm needs to clear the exitinfo1 into the GHCB page. This patch replaces the old method(gpa_write) and clear t
hypervisor: mshv: clear exitinfo1 using mapped ghcb address
After handling the VMG exit vmm needs to clear the exitinfo1 into the GHCB page. This patch replaces the old method(gpa_write) and clear the exitinfo1 using mapped GHCB struct.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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1757d83d | 19-Oct-2024 |
Muminul Islam <muislam@microsoft.com> |
hypervisor: Keep GHCB mapped address for each VCPU on MSHV
For confidential VM on MSHV, GHCB page is the communication method between guest and host. All the CVM exits, VMM needs to read and write t
hypervisor: Keep GHCB mapped address for each VCPU on MSHV
For confidential VM on MSHV, GHCB page is the communication method between guest and host. All the CVM exits, VMM needs to read and write to the GHCB page. MSHV provides an option to remap the page to the root partition. This way VMM could directly read and write to the page and skip extra IOCTL and hypercall. This improvement makes the IO 10% faster.
Signed-off-by: Muminul Islam <muislam@microsoft.com>
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c4063d26 | 29-Nov-2024 |
Ruoqing He <heruoqing@iscas.ac.cn> |
hypervisor: Set pc and a1 for all vcpu
It turns out we need to setup `a0`, `pc` and `a1` for all vcpus before we run them, remove predicates used to set `pc` and `a1` for `vcpu0`.
Signed-off-by: Ru
hypervisor: Set pc and a1 for all vcpu
It turns out we need to setup `a0`, `pc` and `a1` for all vcpus before we run them, remove predicates used to set `pc` and `a1` for `vcpu0`.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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9006013c | 29-Nov-2024 |
Ruoqing He <heruoqing@iscas.ac.cn> |
hypervisor: Tune Vaia trait to work with fdt setup
Previous `Vaia` implementation uses types as it is, thus the property string generated for fdt setup requires additional type conversion. Change th
hypervisor: Tune Vaia trait to work with fdt setup
Previous `Vaia` implementation uses types as it is, thus the property string generated for fdt setup requires additional type conversion. Change the types used in the methods of `Vaia` trait to provide a concise fdt setup process.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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fbe1cd64 | 06-Nov-2024 |
Ruoqing He <heruoqing@iscas.ac.cn> |
hypervisor: kvm: Add g/set_regs unit-test on riscv64
Add unit-test to make sure get_regs and set_regs on riscv64 architecture work as expected, effectively avoiding typos in register names.
Signed-
hypervisor: kvm: Add g/set_regs unit-test on riscv64
Add unit-test to make sure get_regs and set_regs on riscv64 architecture work as expected, effectively avoiding typos in register names.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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76256230 | 09-Oct-2024 |
Ruoqing He <heruoqing@iscas.ac.cn> |
hypervisor: kvm: Complement `create_standard_regs`
Complement `create_standard_regs` implementation on RISC-V platform to work with `From` trait of `kvm_riscv_core`.
Signed-off-by: Ruoqing He <heru
hypervisor: kvm: Complement `create_standard_regs`
Complement `create_standard_regs` implementation on RISC-V platform to work with `From` trait of `kvm_riscv_core`.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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8cd80ea3 | 09-Oct-2024 |
Ruoqing He <heruoqing@iscas.ac.cn> |
hypervisor: Introduce RISC-V architecture
Introduce cpu, vm, kvm, arch module RISC-V platform support. Add macro definitions to implement methods interacting with RISC-V registers.
Signed-off-by: R
hypervisor: Introduce RISC-V architecture
Introduce cpu, vm, kvm, arch module RISC-V platform support. Add macro definitions to implement methods interacting with RISC-V registers.
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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