hypervisor: Fix AIA IMSIC attr calculation

The IMSIC attr of RISC-V AIA is wrongly configured to start from 0, which
would error out with `os error 22` (invalid argument).

```console
Error booting

hypervisor: Fix AIA IMSIC attr calculation

The IMSIC attr of RISC-V AIA is wrongly configured to start from 0, which
would error out with `os error 22` (invalid argument).

```console
Error booting VM: VmBoot(DeviceManager(CreateInterruptController(CreateAia(CreateVaia(Vaia error SetDeviceAttribute(SetDeviceAttribute(Invalid argument (os error 22))))))))
```

`riscv_imsic_attr_of` should shift `cpu_index` by 1 here to produce
correct IMSIC attr.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: Implement fmt::Display for CpuIdEntry

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

hypervisor: kvm: fix an operator precedence clippy warning

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: Automatically fix operator precedence clippy warning

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>

hypervisor: introduce an mshv_emulator feature

This will become useful when we build the fuzzing target for the
instruction emulator, because there is no need to pull in the rest of
the hypervisor c

hypervisor: introduce an mshv_emulator feature

This will become useful when we build the fuzzing target for the
instruction emulator, because there is no need to pull in the rest of
the hypervisor crate in that situation.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

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hypervisor: emulator: use wrapping arithmetic

Signed-off-by: Wei Liu <liuwe@microsoft.com>

hypervisor: emulator: adjust iced-x86 feature flags

The fastfmt feature and VEX support use techniques that appear to leak
memory in the eye of LLVM's address sanitizer.

While at it, disable a bunc

hypervisor: emulator: adjust iced-x86 feature flags

The fastfmt feature and VEX support use techniques that appear to leak
memory in the eye of LLVM's address sanitizer.

While at it, disable a bunch of instruction set decoding support we
never intend to support.

Signed-off-by: Wei Liu <liuwe@microsoft.com>

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hypervisor: maintain a bitmap for SEV-SNP VM on MSHV

Add a bitmap to MshvVM struct for caching the pages
that the VMM got shared access from the guest.

Signed-off-by: Muminul Islam <muislam@microso

hypervisor: maintain a bitmap for SEV-SNP VM on MSHV

Add a bitmap to MshvVM struct for caching the pages
that the VMM got shared access from the guest.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: use memory size during VM creation

For SEV-SNP VM on MSHV we need to request page access during
IO, we want to avoid such request for the page that have already
been requested. In order

hypervisor: use memory size during VM creation

For SEV-SNP VM on MSHV we need to request page access during
IO, we want to avoid such request for the page that have already
been requested. In order to maintain the bitmap we need the memory size
during bitmap creation.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: mshv: modify GuestRequest handling for CVM

VMM needs to handle VMG exit for guest request. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expen

hypervisor: mshv: modify GuestRequest handling for CVM

VMM needs to handle VMG exit for guest request. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expensive and update the GHCB page using
mapped(root partition) struct.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: mshv: modify MMIO exit handling for CVM

VMM needs to handle VMG exit for MMIO. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expensive and upd

hypervisor: mshv: modify MMIO exit handling for CVM

VMM needs to handle VMG exit for MMIO. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expensive and update the GHCB page using
mapped(root partition) struct.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: mshv: modify IoPort handling for CVM

VMM needs to handle VMG exit for IO Port. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expensive and upd

hypervisor: mshv: modify IoPort handling for CVM

VMM needs to handle VMG exit for IO Port. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expensive and update the GHCB page using
mapped(root partition) struct.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: mshv: modify doorbell page handling for CVM

VMM needs to handle VMG exit for doorbell page. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expe

hypervisor: mshv: modify doorbell page handling for CVM

VMM needs to handle VMG exit for doorbell page. This patch
removes the old method that uses gpa_read/write(IOCTL and hypercall),
which is expensive and update the GHCB page using
mapped(root partition) struct.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: mshv: clear exitinfo1 using mapped ghcb address

After handling the VMG exit vmm needs to clear the exitinfo1
into the GHCB page. This patch replaces the old
method(gpa_write) and clear t

hypervisor: mshv: clear exitinfo1 using mapped ghcb address

After handling the VMG exit vmm needs to clear the exitinfo1
into the GHCB page. This patch replaces the old
method(gpa_write) and clear the exitinfo1 using mapped GHCB struct.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: Keep GHCB mapped address for each VCPU on MSHV

For confidential VM on MSHV, GHCB page is the communication
method between guest and host. All the CVM exits, VMM
needs to read and write t

hypervisor: Keep GHCB mapped address for each VCPU on MSHV

For confidential VM on MSHV, GHCB page is the communication
method between guest and host. All the CVM exits, VMM
needs to read and write to the GHCB page. MSHV provides
an option to remap the page to the root partition. This
way VMM could directly read and write to the page and
skip extra IOCTL and hypercall. This improvement makes
the IO 10% faster.

Signed-off-by: Muminul Islam <muislam@microsoft.com>

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hypervisor: Set pc and a1 for all vcpu

It turns out we need to setup `a0`, `pc` and `a1` for all vcpus before
we run them, remove predicates used to set `pc` and `a1` for `vcpu0`.

Signed-off-by: Ru

hypervisor: Set pc and a1 for all vcpu

It turns out we need to setup `a0`, `pc` and `a1` for all vcpus before
we run them, remove predicates used to set `pc` and `a1` for `vcpu0`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: Tune Vaia trait to work with fdt setup

Previous `Vaia` implementation uses types as it is, thus the property
string generated for fdt setup requires additional type conversion.
Change th

hypervisor: Tune Vaia trait to work with fdt setup

Previous `Vaia` implementation uses types as it is, thus the property
string generated for fdt setup requires additional type conversion.
Change the types used in the methods of `Vaia` trait to provide a
concise fdt setup process.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: kvm: Add g/set_regs unit-test on riscv64

Add unit-test to make sure get_regs and set_regs on riscv64 architecture
work as expected, effectively avoiding typos in register names.

Signed-

hypervisor: kvm: Add g/set_regs unit-test on riscv64

Add unit-test to make sure get_regs and set_regs on riscv64 architecture
work as expected, effectively avoiding typos in register names.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: kvm: Complement `create_standard_regs`

Complement `create_standard_regs` implementation on RISC-V platform to
work with `From` trait of `kvm_riscv_core`.

Signed-off-by: Ruoqing He <heru

hypervisor: kvm: Complement `create_standard_regs`

Complement `create_standard_regs` implementation on RISC-V platform to
work with `From` trait of `kvm_riscv_core`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: Introduce RISC-V architecture

Introduce cpu, vm, kvm, arch module RISC-V platform support. Add macro
definitions to implement methods interacting with RISC-V registers.

Signed-off-by: R

hypervisor: Introduce RISC-V architecture

Introduce cpu, vm, kvm, arch module RISC-V platform support. Add macro
definitions to implement methods interacting with RISC-V registers.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

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hypervisor: vm: Introduce RISC-V Vm trait

Introduce RISC-V specific Vm traits and error variant, disable
`create_irq_chip` on RISC-V platform.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

hypervisor: cpu: Introduce RISC-V Vcpu trait

Add RISC-V specific Vcpu trait. Disable `set_guest_debug` on RISC-V
platform.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

hypervisor: kvm: Integrate riscv64 regs & AIA

Incorporates riscv64 register interaction and AIA creation to kvm
module. Complete `Vcpu` trait on RISC-V platform.

Signed-off-by: Ruoqing He <heruoqin

hypervisor: kvm: Integrate riscv64 regs & AIA

Incorporates riscv64 register interaction and AIA creation to kvm
module. Complete `Vcpu` trait on RISC-V platform.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

show more ...

hypervisor: cpu: Introduce RISC-V specific error

Add error variants specific to RISC-V architecture.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>

hypervisor: kvm: Introduce AIA creation

Implement definition required to work with KVM in-kernel AIA device,
construction procedure of AIA.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>